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09 Oct 2022 23:42:28 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Sun, 9 Oct 2022 23:42:27 -0700 Received: from wendy (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12 via Frontend Transport; Sun, 9 Oct 2022 23:42:26 -0700 Date: Mon, 10 Oct 2022 07:42:04 +0100 From: Conor Dooley To: Vernon Yang CC: , , , , , , Subject: Re: [PATCH] RISC-V: KVM: fixup undefined reference to riscv_cbom_block_size Message-ID: References: <202210091222.xuZquaM9-lkp@intel.com> <20221010013329.199167-1-vernon2gm@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20221010013329.199167-1-vernon2gm@gmail.com> ARC-Authentication-Results: i=1; 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dkim=pass header.d=microchip.com header.s=mchp header.b=tsEozuy3; spf=pass (imf11.hostedemail.com: domain of Conor.Dooley@microchip.com designates 68.232.153.233 as permitted sender) smtp.mailfrom=Conor.Dooley@microchip.com; dmarc=pass (policy=quarantine) header.from=microchip.com X-Rspamd-Server: rspam10 X-Stat-Signature: zb1ogjpyh67bck9goxck6g3gstay8cti X-HE-Tag: 1665384149-568932 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000001, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On Mon, Oct 10, 2022 at 09:33:29AM +0800, Vernon Yang wrote: > When some RISC-V compilers do not support the Zicbom extension, > the build system auto disable the CONFIG_RISCV_ISA_ZICBOM, so the > source code of the relevant function is not compiled, resulting > in the definition of the riscv_cbom_block_size variable cannot > be found Hmm, my understanding was that riscv_cbom_block_size was not supposed to depend on CONFIG_RISCV_ISA_ZICBOM because the thead is able to use it even if the toolchain does not support it. The code in cacheflush.h looks like: extern unsigned int riscv_cbom_block_size; #ifdef CONFIG_RISCV_ISA_ZICBOM void riscv_init_cbom_blocksize(void); #else static inline void riscv_init_cbom_blocksize(void) { } #endif #ifdef CONFIG_RISCV_DMA_NONCOHERENT void riscv_noncoherent_supported(void); #endif It's early and I only had a quick look but I think that this is not defined because RISCV_DMA_NONCOHERENT is not defined, not because of RISCV_ISA_ZICBOM. I'm not the KVM maintainer, but I dislike #ifdefery in c files, so it'd be nice I think to sort this out in the header and not have to worry about guarding the variable. That's my 0.02 €.. Thanks, Conor. > So add conditional compilation to fix it > > Reported-by: kernel test robot > Signed-off-by: Vernon Yang > --- > arch/riscv/kvm/vcpu.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c > index a032c4f0d600..08a6c3cb695d 100644 > --- a/arch/riscv/kvm/vcpu.c > +++ b/arch/riscv/kvm/vcpu.c > @@ -256,7 +256,7 @@ static int kvm_riscv_vcpu_get_reg_config(struct kvm_vcpu *vcpu, > unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | > KVM_REG_SIZE_MASK | > KVM_REG_RISCV_CONFIG); > - unsigned long reg_val; > + unsigned long reg_val = 0; > > if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) > return -EINVAL; > @@ -268,7 +268,9 @@ static int kvm_riscv_vcpu_get_reg_config(struct kvm_vcpu *vcpu, > case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size): > if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOM)) > return -EINVAL; > +#ifdef CONFIG_RISCV_ISA_ZICBOM > reg_val = riscv_cbom_block_size; > +#endif > break; > default: > return -EINVAL; > -- > 2.25.1 > >