From: Gregory Price <gregory.price@memverge.com>
To: Dan Williams <dan.j.williams@intel.com>
Cc: linux-cxl@vger.kernel.org, David Hildenbrand <david@redhat.com>,
Kees Cook <keescook@chromium.org>,
stable@vger.kernel.org, Dave Hansen <dave.hansen@linux.intel.com>,
Michal Hocko <mhocko@suse.com>,
linux-mm@kvack.org, linux-acpi@vger.kernel.org
Subject: Re: [PATCH 00/18] CXL RAM and the 'Soft Reserved' => 'System RAM' default
Date: Mon, 6 Feb 2023 00:36:11 -0500 [thread overview]
Message-ID: <Y+CRyz0eFKfERZLD@memverge.com> (raw)
In-Reply-To: <167564534874.847146.5222419648551436750.stgit@dwillia2-xfh.jf.intel.com>
On Sun, Feb 05, 2023 at 05:02:29PM -0800, Dan Williams wrote:
> Summary:
> --------
>
> CXL RAM support allows for the dynamic provisioning of new CXL RAM
> regions, and more routinely, assembling a region from an existing
> configuration established by platform-firmware. The latter is motivated
> by CXL memory RAS (Reliability, Availability and Serviceability)
> support, that requires associating device events with System Physical
> Address ranges and vice versa.
>
> The 'Soft Reserved' policy rework arranges for performance
> differentiated memory like CXL attached DRAM, or high-bandwidth memory,
> to be designated for 'System RAM' by default, rather than the device-dax
> dedicated access mode. That current device-dax default is confusing and
> surprising for the Pareto of users that do not expect memory to be
> quarantined for dedicated access by default. Most users expect all
> 'System RAM'-capable memory to show up in FREE(1).
Leverage the same QEMU branch, machine, and configuration as my prior
tests, i'm now experiencing a kernel panic on boot. Will debug a bit
in the morning, but here is the stack trace i'm seeing
Saw this in both 1 and 2 root port configurations
(note: I also have the region reset issue previously discussed on top of
your branch).
QEMU configuration:
sudo /opt/qemu-cxl/bin/qemu-system-x86_64 \
-drive file=/var/lib/libvirt/images/cxl.qcow2,format=qcow2,index=0,media=disk,id=hd \
-m 2G,slots=4,maxmem=4G \
-smp 4 \
-machine type=q35,accel=kvm,cxl=on \
-enable-kvm \
-nographic \
-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 \
-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,port=0,slot=0 \
-object memory-backend-file,id=mem0,mem-path=/tmp/mem0,size=1G,share=true \
-device cxl-type3,bus=rp0,volatile-memdev=mem0,id=cxl-mem0 \
-M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.size=1G
[ 13.936817] Call Trace:
[ 13.970691] <TASK>
[ 13.990690] device_add+0x39d/0x9a0
[ 14.024690] ? kobject_set_name_vargs+0x6d/0x90
[ 14.066690] ? dev_set_name+0x4b/0x60
[ 14.090691] devm_cxl_add_port+0x29a/0x4d0
[ 14.135946] cxl_acpi_probe+0xd9/0x2f0
[ 14.167691] ? device_pm_check_callbacks+0x36/0x100
[ 14.203691] platform_probe+0x44/0x90
[ 14.247691] really_probe+0xde/0x380
[ 14.277690] ? pm_runtime_barrier+0x50/0x90
[ 14.324693] __driver_probe_device+0x78/0x170
[ 14.356694] driver_probe_device+0x1f/0x90
[ 14.396692] __driver_attach+0xce/0x1c0
[ 14.435691] ? __pfx___driver_attach+0x10/0x10
[ 14.471692] bus_for_each_dev+0x73/0xa0
[ 14.508693] bus_add_driver+0x1ae/0x200
[ 14.551691] driver_register+0x89/0xe0
[ 14.587691] ? __pfx_cxl_acpi_init+0x10/0x10
[ 14.625690] do_one_initcall+0x59/0x230
[ 14.814691] kernel_init_freeable+0x204/0x24e
[ 14.846710] ? __pfx_kernel_init+0x10/0x10
[ 14.899692] kernel_init+0x16/0x140
[ 14.954691] ret_from_fork+0x2c/0x50
[ 14.986692] </TASK>
[ 15.023689] Modules linked in:
[ 15.057693] CR2: 0000000000000060
[ 15.105691] ---[ end trace 0000000000000000 ]---
[ 15.162837] RIP: 0010:bus_add_device+0x5b/0x150
[ 15.217693] Code: 49 8b 74 24 20 48 89 df e8 92 88 ff ff 89 c5 85 c0 75 3b 48 8b 53 50 48 85 d2 75 03 48 8b 13 49 8b 84 24 a8 00 00 00 48 89 0
[ 15.427859] RSP: 0000:ffffbd2a40013bc0 EFLAGS: 00010246
[ 15.475692] RAX: 0000000000000000 RBX: ffff955c419e1800 RCX: 0000000000000000
[ 15.591691] RDX: ffff955c41921778 RSI: ffff955c419e1800 RDI: ffff955c419e1800
[ 15.703693] RBP: 0000000000000000 R08: 0000000000000228 R09: ffff955c4119e550
[ 15.802711] R10: ffff955c414bedc8 R11: 0000000000000000 R12: ffffffff9e259d60
[ 15.907692] R13: ffffffff9d3cee40 R14: ffff955c419e1800 R15: ffff955c41f06010
[ 15.983693] FS: 0000000000000000(0000) GS:ffff955cbdd00000(0000) knlGS:0000000000000000
[ 16.126698] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[ 16.206694] CR2: 0000000000000060 CR3: 0000000036010000 CR4: 00000000000006e0
[ 16.347694] Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000009
[ 16.348686] ---[ end Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000009 ]---
next prev parent reply other threads:[~2023-02-06 5:36 UTC|newest]
Thread overview: 111+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-06 1:02 Dan Williams
2023-02-06 1:02 ` [PATCH 01/18] cxl/Documentation: Update references to attributes added in v6.0 Dan Williams
2023-02-06 15:17 ` Jonathan Cameron
2023-02-06 16:37 ` Gregory Price
2023-02-06 17:27 ` [PATCH 1/18] " Davidlohr Bueso
2023-02-06 19:15 ` [PATCH 01/18] " Ira Weiny
2023-02-06 21:04 ` Dave Jiang
2023-02-09 0:20 ` Verma, Vishal L
2023-02-06 1:02 ` [PATCH 02/18] cxl/region: Add a mode attribute for regions Dan Williams
2023-02-06 15:46 ` Jonathan Cameron
2023-02-06 17:47 ` Dan Williams
2023-02-06 16:39 ` Gregory Price
2023-02-06 19:16 ` Ira Weiny
2023-02-06 21:05 ` Dave Jiang
2023-02-09 0:22 ` Verma, Vishal L
2023-02-06 1:02 ` [PATCH 03/18] cxl/region: Support empty uuids for non-pmem regions Dan Williams
2023-02-06 15:54 ` Jonathan Cameron
2023-02-06 18:07 ` Dan Williams
2023-02-06 19:22 ` Ira Weiny
2023-02-06 19:35 ` Dan Williams
2023-02-09 0:24 ` Verma, Vishal L
2023-02-06 1:02 ` [PATCH 04/18] cxl/region: Validate region mode vs decoder mode Dan Williams
2023-02-06 16:02 ` Jonathan Cameron
2023-02-06 18:14 ` Dan Williams
2023-02-06 16:44 ` Gregory Price
2023-02-06 21:51 ` Dan Williams
2023-02-06 19:55 ` Gregory Price
2023-02-06 19:23 ` Ira Weiny
2023-02-06 22:16 ` Dave Jiang
2023-02-09 0:25 ` Verma, Vishal L
2023-02-06 1:02 ` [PATCH 05/18] cxl/region: Add volatile region creation support Dan Williams
2023-02-06 16:18 ` Jonathan Cameron
2023-02-06 18:19 ` Dan Williams
2023-02-06 16:55 ` Gregory Price
2023-02-06 21:57 ` Dan Williams
2023-02-06 19:56 ` Gregory Price
2023-02-06 19:25 ` Ira Weiny
2023-02-06 22:31 ` Dave Jiang
2023-02-06 22:37 ` Dan Williams
2023-02-09 1:02 ` Verma, Vishal L
2023-02-06 1:03 ` [PATCH 06/18] cxl/region: Refactor attach_target() for autodiscovery Dan Williams
2023-02-06 17:06 ` Jonathan Cameron
2023-02-06 18:48 ` Dan Williams
2023-02-06 19:26 ` Ira Weiny
2023-02-06 22:41 ` Dave Jiang
2023-02-09 1:09 ` Verma, Vishal L
2023-02-06 1:03 ` [PATCH 07/18] cxl/region: Move region-position validation to a helper Dan Williams
2023-02-06 17:44 ` Ira Weiny
2023-02-06 19:15 ` Dan Williams
2023-02-08 12:30 ` Jonathan Cameron
2023-02-09 4:09 ` Dan Williams
2023-02-09 4:26 ` Dan Williams
2023-02-09 11:07 ` Jonathan Cameron
2023-02-09 20:52 ` Dan Williams
2023-02-09 19:45 ` Verma, Vishal L
2023-02-06 1:03 ` [PATCH 08/18] kernel/range: Uplevel the cxl subsystem's range_contains() helper Dan Williams
2023-02-06 17:02 ` Gregory Price
2023-02-06 22:01 ` Dan Williams
2023-02-06 19:28 ` Ira Weiny
2023-02-06 23:41 ` Dave Jiang
2023-02-08 12:32 ` Jonathan Cameron
2023-02-09 19:47 ` Verma, Vishal L
2023-02-06 1:03 ` [PATCH 09/18] cxl/region: Enable CONFIG_CXL_REGION to be toggled Dan Williams
2023-02-06 17:03 ` Gregory Price
2023-02-06 23:57 ` Dave Jiang
2023-02-08 12:36 ` Jonathan Cameron
2023-02-09 20:17 ` Verma, Vishal L
2023-02-06 1:03 ` [PATCH 10/18] cxl/region: Fix passthrough-decoder detection Dan Williams
2023-02-06 5:38 ` Greg KH
2023-02-06 17:22 ` Dan Williams
2023-02-07 0:00 ` Dave Jiang
2023-02-08 12:44 ` Jonathan Cameron
2023-02-09 20:28 ` Verma, Vishal L
2023-02-06 1:03 ` [PATCH 11/18] cxl/region: Add region autodiscovery Dan Williams
2023-02-06 19:02 ` Ira Weiny
2023-02-07 23:54 ` Dave Jiang
2023-02-08 17:07 ` Jonathan Cameron
2023-02-09 4:07 ` Dan Williams
2023-02-06 1:03 ` [PATCH 12/18] tools/testing/cxl: Define a fixed volatile configuration to parse Dan Williams
2023-02-08 17:31 ` Jonathan Cameron
2023-02-09 20:50 ` Dan Williams
2023-02-06 1:03 ` [PATCH 13/18] dax/hmem: Move HMAT and Soft reservation probe initcall level Dan Williams
2023-02-06 1:03 ` [PATCH 14/18] dax/hmem: Drop unnecessary dax_hmem_remove() Dan Williams
2023-02-06 17:15 ` Gregory Price
2023-02-08 17:33 ` Jonathan Cameron
2023-02-06 1:03 ` [PATCH 15/18] dax/hmem: Convey the dax range via memregion_info() Dan Williams
2023-02-08 17:35 ` Jonathan Cameron
2023-02-06 1:03 ` [PATCH 16/18] dax/hmem: Move hmem device registration to dax_hmem.ko Dan Williams
2023-02-06 1:04 ` [PATCH 17/18] dax: Assign RAM regions to memory-hotplug by default Dan Williams
2023-02-06 17:26 ` Gregory Price
2023-02-06 22:15 ` Dan Williams
2023-02-06 19:05 ` Gregory Price
2023-02-06 23:20 ` Dan Williams
2023-02-06 1:04 ` [PATCH 18/18] cxl/dax: Create dax devices for CXL RAM regions Dan Williams
2023-02-06 5:36 ` Gregory Price [this message]
2023-02-06 16:40 ` [PATCH 00/18] CXL RAM and the 'Soft Reserved' => 'System RAM' default Davidlohr Bueso
2023-02-06 18:23 ` Dan Williams
2023-02-06 17:29 ` Dan Williams
2023-02-06 17:18 ` Davidlohr Bueso
[not found] ` <CGME20230208173730uscas1p2af3a9eeb8946dfa607b190c079a49653@uscas1p2.samsung.com>
2023-02-08 17:37 ` Fan Ni
2023-02-09 4:56 ` Dan Williams
2023-02-13 12:13 ` David Hildenbrand
2023-02-14 18:45 ` Dan Williams
2023-02-14 18:27 ` Gregory Price
2023-02-14 18:39 ` Dan Williams
2023-02-14 19:01 ` Gregory Price
2023-02-14 21:18 ` Jonathan Cameron
2023-02-14 21:51 ` Gregory Price
2023-02-14 21:54 ` Gregory Price
2023-02-15 10:03 ` Jonathan Cameron
2023-02-18 9:47 ` Gregory Price
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