From: Michael Kelley <mhklinux@outlook.com>
To: "riel@surriel.com" <riel@surriel.com>, "x86@kernel.org" <x86@kernel.org>
Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"bp@alien8.de" <bp@alien8.de>,
"peterz@infradead.org" <peterz@infradead.org>,
"dave.hansen@linux.intel.com" <dave.hansen@linux.intel.com>,
"zhengqi.arch@bytedance.com" <zhengqi.arch@bytedance.com>,
"nadav.amit@gmail.com" <nadav.amit@gmail.com>,
"thomas.lendacky@amd.com" <thomas.lendacky@amd.com>,
"kernel-team@meta.com" <kernel-team@meta.com>,
"linux-mm@kvack.org" <linux-mm@kvack.org>,
"akpm@linux-foundation.org" <akpm@linux-foundation.org>,
"jackmanb@google.com" <jackmanb@google.com>,
"jannh@google.com" <jannh@google.com>,
"andrew.cooper3@citrix.com" <andrew.cooper3@citrix.com>
Subject: RE: [PATCH v10 00/12] AMD broadcast TLB invalidation
Date: Wed, 12 Feb 2025 20:35:46 +0000 [thread overview]
Message-ID: <SN6PR02MB4157BA0DCCBFB5D67CF78B69D4FC2@SN6PR02MB4157.namprd02.prod.outlook.com> (raw)
In-Reply-To: <20250211210823.242681-1-riel@surriel.com>
From: riel@surriel.com <riel@surriel.com> Sent: Tuesday, February 11, 2025 1:08 PM
>
> Add support for broadcast TLB invalidation using AMD's INVLPGB instruction.
>
> This allows the kernel to invalidate TLB entries on remote CPUs without
> needing to send IPIs, without having to wait for remote CPUs to handle
> those interrupts, and with less interruption to what was running on
> those CPUs.
>
> Because x86 PCID space is limited, and there are some very large
> systems out there, broadcast TLB invalidation is only used for
> processes that are active on 3 or more CPUs, with the threshold
> being gradually increased the more the PCID space gets exhausted.
>
> Combined with the removal of unnecessary lru_add_drain calls
> (see https://lkml.org/lkml/2024/12/19/1388) this results in a
> nice performance boost for the will-it-scale tlb_flush2_threads
> test on an AMD Milan system with 36 cores:
>
> - vanilla kernel: 527k loops/second
> - lru_add_drain removal: 731k loops/second
> - only INVLPGB: 527k loops/second
> - lru_add_drain + INVLPGB: 1157k loops/second
>
> Profiling with only the INVLPGB changes showed while
> TLB invalidation went down from 40% of the total CPU
> time to only around 4% of CPU time, the contention
> simply moved to the LRU lock.
>
> Fixing both at the same time about doubles the
> number of iterations per second from this case.
>
> Some numbers closer to real world performance
> can be found at Phoronix, thanks to Michael:
>
> https://www.phoronix.com/news/AMD-INVLPGB-Linux-Benefits
>
> My current plan is to implement support for Intel's RAR
> (Remote Action Request) TLB flushing in a follow-up series,
> after this thing has been merged into -tip. Making things
> any larger would just be unwieldy for reviewers.
>
> v10:
> - simplify partial pages with min(nr, 1) in the invlpgb loop (Peter)
> - document x86 paravirt, AMD invlpgb, and ARM64 flush without IPI (Brendan)
> - remove IS_ENABLED(CONFIG_X86_BROADCAST_TLB_FLUSH) (Brendan)
> - various cleanups (Brendan)
> v9:
> - print warning when start or end address was rounded (Peter)
> - in the reclaim code, tlbsync at context switch time (Peter)
> - fix !CONFIG_CPU_SUP_AMD compile error in arch_tlbbatch_add_pending (Jan)
> v8:
> - round start & end to handle non-page-aligned callers (Steven & Jan)
> - fix up changelog & add tested-by tags (Manali)
> v7:
> - a few small code cleanups (Nadav)
> - fix spurious VM_WARN_ON_ONCE in mm_global_asid
> - code simplifications & better barriers (Peter & Dave)
> v6:
> - fix info->end check in flush_tlb_kernel_range (Michael)
> - disable broadcast TLB flushing on 32 bit x86
> v5:
> - use byte assembly for compatibility with older toolchains (Borislav, Michael)
> - ensure a panic on an invalid number of extra pages (Dave, Tom)
> - add cant_migrate() assertion to tlbsync (Jann)
> - a bunch more cleanups (Nadav)
> - key TCE enabling off X86_FEATURE_TCE (Andrew)
> - fix a race between reclaim and ASID transition (Jann)
> v4:
> - Use only bitmaps to track free global ASIDs (Nadav)
> - Improved AMD initialization (Borislav & Tom)
> - Various naming and documentation improvements (Peter, Nadav, Tom, Dave)
> - Fixes for subtle race conditions (Jann)
> v3:
> - Remove paravirt tlb_remove_table call (thank you Qi Zheng)
> - More suggested cleanups and changelog fixes by Peter and Nadav
> v2:
> - Apply suggestions by Peter and Borislav (thank you!)
> - Fix bug in arch_tlbbatch_flush, where we need to do both
> the TLBSYNC, and flush the CPUs that are in the cpumask.
> - Some updates to comments and changelogs based on questions.
>
Tested this series in an Azure Confidential VM based on SEV-SNP,
which is running on Hyper-V and exposes INVLPGB in the guest VM.
I applied the patches to 6.13.0 with one minor fixup, but did not
include the patch to remove unnecessary lru_add_drain calls.
I also added some custom telemetry to see when INVLPGB is
being used vs. Hyper-V's paravirt hypercalls for TLB flushing.
I did not see any problems. The custom telemetry looked about
as I expected, showing a mix of INVLPGB and the PV hypercalls.
So for the series:
Tested-by: Michael Kelley <mhklinux@outlook.com>
prev parent reply other threads:[~2025-02-12 20:35 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-11 21:07 Rik van Riel
2025-02-11 21:07 ` [PATCH v10 01/12] x86/mm: make MMU_GATHER_RCU_TABLE_FREE unconditional Rik van Riel
2025-02-11 21:07 ` [PATCH v10 02/12] x86/mm: remove pv_ops.mmu.tlb_remove_table call Rik van Riel
2025-02-11 21:07 ` [PATCH v10 03/12] x86/mm: consolidate full flush threshold decision Rik van Riel
2025-02-11 21:07 ` [PATCH v10 04/12] x86/mm: get INVLPGB count max from CPUID Rik van Riel
2025-02-11 21:08 ` [PATCH v10 05/12] x86/mm: add INVLPGB support code Rik van Riel
2025-02-11 21:08 ` [PATCH v10 06/12] x86/mm: use INVLPGB for kernel TLB flushes Rik van Riel
2025-02-11 21:08 ` [PATCH v10 07/12] x86/mm: use INVLPGB in flush_tlb_all Rik van Riel
2025-02-11 21:08 ` [PATCH v10 08/12] x86/mm: use broadcast TLB flushing for page reclaim TLB flushing Rik van Riel
2025-02-11 21:08 ` [PATCH v10 09/12] x86/mm: enable broadcast TLB invalidation for multi-threaded processes Rik van Riel
2025-02-12 9:54 ` Peter Zijlstra
2025-02-12 10:22 ` Peter Zijlstra
2025-02-12 10:42 ` Peter Zijlstra
2025-02-12 12:07 ` Nadav Amit
2025-02-12 13:28 ` Brendan Jackman
2025-02-11 21:08 ` [PATCH v10 10/12] x86/mm: do targeted broadcast flushing from tlbbatch code Rik van Riel
2025-02-12 13:32 ` Brendan Jackman
2025-02-11 21:08 ` [PATCH v10 11/12] x86/mm: enable AMD translation cache extensions Rik van Riel
2025-02-11 21:08 ` [PATCH v10 12/12] x86/mm: only invalidate final translations with INVLPGB Rik van Riel
2025-02-12 10:23 ` [PATCH v10 00/12] AMD broadcast TLB invalidation Peter Zijlstra
2025-02-12 10:44 ` Brendan Jackman
2025-02-12 10:59 ` Peter Zijlstra
2025-02-12 15:39 ` Rik van Riel
2025-02-13 13:03 ` Borislav Petkov
2025-02-12 16:30 ` Sean Christopherson
2025-02-12 20:35 ` Michael Kelley [this message]
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