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From: Michael Kelley <mhklinux@outlook.com>
To: "riel@surriel.com" <riel@surriel.com>, "x86@kernel.org" <x86@kernel.org>
Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"bp@alien8.de" <bp@alien8.de>,
	"peterz@infradead.org" <peterz@infradead.org>,
	"dave.hansen@linux.intel.com" <dave.hansen@linux.intel.com>,
	"zhengqi.arch@bytedance.com" <zhengqi.arch@bytedance.com>,
	"nadav.amit@gmail.com" <nadav.amit@gmail.com>,
	"thomas.lendacky@amd.com" <thomas.lendacky@amd.com>,
	"kernel-team@meta.com" <kernel-team@meta.com>,
	"linux-mm@kvack.org" <linux-mm@kvack.org>,
	"akpm@linux-foundation.org" <akpm@linux-foundation.org>,
	"jannh@google.com" <jannh@google.com>,
	"andrew.cooper3@citrix.com" <andrew.cooper3@citrix.com>,
	Dave Hansen <dave.hansen@intel.com>
Subject: RE: [PATCH v5 03/12] x86/mm: consolidate full flush threshold decision
Date: Fri, 17 Jan 2025 19:23:03 +0000	[thread overview]
Message-ID: <SN6PR02MB41574BB1004E584168B8D30BD41B2@SN6PR02MB4157.namprd02.prod.outlook.com> (raw)
In-Reply-To: <20250116023127.1531583-4-riel@surriel.com>

From: riel@surriel.com <riel@surriel.com> Sent: Wednesday, January 15, 2025 6:30 PM
> 
> Reduce code duplication by consolidating the decision point
> for whether to do individual invalidations or a full flush
> inside get_flush_tlb_info.
> 
> Signed-off-by: Rik van Riel <riel@surriel.com>
> Suggested-by: Dave Hansen <dave.hansen@intel.com>
> ---
>  arch/x86/mm/tlb.c | 43 ++++++++++++++++++++-----------------------
>  1 file changed, 20 insertions(+), 23 deletions(-)
> 
> diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c
> index 6cf881a942bb..2f38cf95dee3 100644
> --- a/arch/x86/mm/tlb.c
> +++ b/arch/x86/mm/tlb.c

[snip]

> @@ -1089,22 +1089,19 @@ static void do_kernel_range_flush(void *info)
> 
>  void flush_tlb_kernel_range(unsigned long start, unsigned long end)
>  {
> -	/* Balance as user space task's flush, a bit conservative */
> -	if (end == TLB_FLUSH_ALL ||
> -	    (end - start) > tlb_single_page_flush_ceiling << PAGE_SHIFT) {
> -		on_each_cpu(do_flush_tlb_all, NULL, 1);
> -	} else {
> -		struct flush_tlb_info *info;
> +	struct flush_tlb_info *info;
> 
> -		preempt_disable();
> -		info = get_flush_tlb_info(NULL, start, end, 0, false,
> -					  TLB_GENERATION_INVALID);
> +	guard(preempt)();
> +
> +	info = get_flush_tlb_info(NULL, start, end, PAGE_SHIFT, false,
> +				  TLB_GENERATION_INVALID);
> 
> +	if (end == TLB_FLUSH_ALL)

This needs to test "info->end", not "end".

In my VM on Hyper-V *without* INVLPGB support, the bug causes
boot to hang as it tries to individually flush each page in the
[0, TLB_FLUSH_ALL] range. :-)

Michael

> +		on_each_cpu(do_flush_tlb_all, NULL, 1);
> +	else
>  		on_each_cpu(do_kernel_range_flush, info, 1);
> 
> -		put_flush_tlb_info();
> -		preempt_enable();
> -	}
> +	put_flush_tlb_info();
>  }
> 
>  /*


  reply	other threads:[~2025-01-17 19:23 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-16  2:30 [PATCH v5 00/12] AMD broadcast TLB invalidation Rik van Riel
2025-01-16  2:30 ` [PATCH v5 01/12] x86/mm: make MMU_GATHER_RCU_TABLE_FREE unconditional Rik van Riel
2025-01-16  2:30 ` [PATCH v5 02/12] x86/mm: remove pv_ops.mmu.tlb_remove_table call Rik van Riel
2025-01-16  2:30 ` [PATCH v5 03/12] x86/mm: consolidate full flush threshold decision Rik van Riel
2025-01-17 19:23   ` Michael Kelley [this message]
2025-01-17 19:32     ` Rik van Riel
2025-01-16  2:30 ` [PATCH v5 04/12] x86/mm: get INVLPGB count max from CPUID Rik van Riel
2025-01-16  2:30 ` [PATCH v5 05/12] x86/mm: add INVLPGB support code Rik van Riel
2025-01-16  2:30 ` [PATCH v5 06/12] x86/mm: use INVLPGB for kernel TLB flushes Rik van Riel
2025-01-16  2:30 ` [PATCH v5 07/12] x86/tlb: use INVLPGB in flush_tlb_all Rik van Riel
2025-01-16  2:30 ` [PATCH v5 08/12] x86/mm: use broadcast TLB flushing for page reclaim TLB flushing Rik van Riel
2025-01-16  2:30 ` [PATCH v5 09/12] x86/mm: enable broadcast TLB invalidation for multi-threaded processes Rik van Riel
2025-01-16  2:30 ` [PATCH v5 10/12] x86,tlb: do targeted broadcast flushing from tlbbatch code Rik van Riel
2025-01-20  9:56   ` Nadav Amit
2025-01-20 14:02     ` Rik van Riel
2025-01-20 14:14       ` Nadav Amit
2025-01-20 16:11         ` Rik van Riel
2025-01-20 17:09           ` Nadav Amit
2025-01-20 17:11             ` Rik van Riel
2025-01-20 17:50               ` Nadav Amit
2025-01-20 17:56                 ` Rik van Riel
2025-01-20 18:56                   ` Nadav Amit
2025-01-21  2:33                     ` Rik van Riel
2025-01-16  2:30 ` [PATCH v5 11/12] x86/mm: enable AMD translation cache extensions Rik van Riel
2025-01-16  2:30 ` [PATCH v5 12/12] x86/mm: only invalidate final translations with INVLPGB Rik van Riel
2025-01-16 18:14 ` [PATCH v5 00/12] AMD broadcast TLB invalidation Michael Kelley
2025-01-16 22:37   ` Peter Zijlstra
2025-01-17  0:00     ` Andrew Cooper
2025-01-21 10:45       ` Peter Zijlstra
2025-01-21 17:14   ` Dave Hansen
2025-01-21 21:24     ` Michael Kelley
2025-01-21 17:22   ` Jann Horn
2025-01-21 21:39     ` Michael Kelley
2025-01-21 21:56       ` Jann Horn

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