From: Michael Kelley <mhklinux@outlook.com>
To: Dave Hansen <dave.hansen@intel.com>,
"riel@surriel.com" <riel@surriel.com>,
"x86@kernel.org" <x86@kernel.org>
Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"bp@alien8.de" <bp@alien8.de>,
"peterz@infradead.org" <peterz@infradead.org>,
"dave.hansen@linux.intel.com" <dave.hansen@linux.intel.com>,
"zhengqi.arch@bytedance.com" <zhengqi.arch@bytedance.com>,
"nadav.amit@gmail.com" <nadav.amit@gmail.com>,
"thomas.lendacky@amd.com" <thomas.lendacky@amd.com>,
"kernel-team@meta.com" <kernel-team@meta.com>,
"linux-mm@kvack.org" <linux-mm@kvack.org>,
"akpm@linux-foundation.org" <akpm@linux-foundation.org>,
"jannh@google.com" <jannh@google.com>,
"andrew.cooper3@citrix.com" <andrew.cooper3@citrix.com>
Subject: RE: [PATCH v5 00/12] AMD broadcast TLB invalidation
Date: Tue, 21 Jan 2025 21:24:15 +0000 [thread overview]
Message-ID: <SN6PR02MB41573E61AACDF5FBBB541A05D4E62@SN6PR02MB4157.namprd02.prod.outlook.com> (raw)
In-Reply-To: <01cba8ef-b68f-4074-9a7b-7258eaee3893@intel.com>
From: Dave Hansen <dave.hansen@intel.com> Sent: Tuesday, January 21, 2025 9:15 AM
>
> On 1/16/25 10:14, Michael Kelley wrote:
> > So CoCo VMs may still use the paravirtualization that makes
> > hypercalls to do TLB flushes. It's future work to *always* use
> > INVLPGB (if available) in a CoCo VM.
>
> How would this actually work, though?
>
> One of the reasons that we have the whole TLB_NR_DYN_ASIDS mechanism is
> that picking a PCID to shove in CR3 is an entirely CPU local operation.
> The PCID is in a CPU-local namespace and nobody else cares what it is.
>
> Rik obviously now has a system-wide set of IDs which are globally
> visible and globally valid. But his mechanism is also a bit choosy so
> that the global resource management doesn't get to be a choke point.
>
> But if we move to INVLPGB-only, we're all of a sudden *forced* to do
> some kind of wide global resource management, even for single-threaded
> processes. Rik doesn't have a scheme for that in the current set.
>
> So I think this would be a whole separate conversation from this series.
Yes, I agree completely.
The topic initially came up when I was wondering whether INVLPGB is
ever enabled in a VM, in which case Rik's patch set would be active in
the VM. I was somewhat surprised to find that INVLPGB *is* enabled
in Azure CoCo VMs. But that turned out to be for the entirely different
use case of avoiding a dependency on the untrusted hypervisor to do
TLB flushes.
The thread perhaps went a bit too far afield from Rik's patch set, but
there's value in having some discussion about the CoCo use case.
Michael
next prev parent reply other threads:[~2025-01-21 21:24 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-16 2:30 Rik van Riel
2025-01-16 2:30 ` [PATCH v5 01/12] x86/mm: make MMU_GATHER_RCU_TABLE_FREE unconditional Rik van Riel
2025-01-16 2:30 ` [PATCH v5 02/12] x86/mm: remove pv_ops.mmu.tlb_remove_table call Rik van Riel
2025-01-16 2:30 ` [PATCH v5 03/12] x86/mm: consolidate full flush threshold decision Rik van Riel
2025-01-17 19:23 ` Michael Kelley
2025-01-17 19:32 ` Rik van Riel
2025-01-16 2:30 ` [PATCH v5 04/12] x86/mm: get INVLPGB count max from CPUID Rik van Riel
2025-01-16 2:30 ` [PATCH v5 05/12] x86/mm: add INVLPGB support code Rik van Riel
2025-01-16 2:30 ` [PATCH v5 06/12] x86/mm: use INVLPGB for kernel TLB flushes Rik van Riel
2025-01-16 2:30 ` [PATCH v5 07/12] x86/tlb: use INVLPGB in flush_tlb_all Rik van Riel
2025-01-16 2:30 ` [PATCH v5 08/12] x86/mm: use broadcast TLB flushing for page reclaim TLB flushing Rik van Riel
2025-01-16 2:30 ` [PATCH v5 09/12] x86/mm: enable broadcast TLB invalidation for multi-threaded processes Rik van Riel
2025-01-16 2:30 ` [PATCH v5 10/12] x86,tlb: do targeted broadcast flushing from tlbbatch code Rik van Riel
2025-01-20 9:56 ` Nadav Amit
2025-01-20 14:02 ` Rik van Riel
2025-01-20 14:14 ` Nadav Amit
2025-01-20 16:11 ` Rik van Riel
2025-01-20 17:09 ` Nadav Amit
2025-01-20 17:11 ` Rik van Riel
2025-01-20 17:50 ` Nadav Amit
2025-01-20 17:56 ` Rik van Riel
2025-01-20 18:56 ` Nadav Amit
2025-01-21 2:33 ` Rik van Riel
2025-01-16 2:30 ` [PATCH v5 11/12] x86/mm: enable AMD translation cache extensions Rik van Riel
2025-01-16 2:30 ` [PATCH v5 12/12] x86/mm: only invalidate final translations with INVLPGB Rik van Riel
2025-01-16 18:14 ` [PATCH v5 00/12] AMD broadcast TLB invalidation Michael Kelley
2025-01-16 22:37 ` Peter Zijlstra
2025-01-17 0:00 ` Andrew Cooper
2025-01-21 10:45 ` Peter Zijlstra
2025-01-21 17:14 ` Dave Hansen
2025-01-21 21:24 ` Michael Kelley [this message]
2025-01-21 17:22 ` Jann Horn
2025-01-21 21:39 ` Michael Kelley
2025-01-21 21:56 ` Jann Horn
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