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From: Ankit Agrawal <ankita@nvidia.com>
To: Jason Gunthorpe <jgg@nvidia.com>
Cc: "maz@kernel.org" <maz@kernel.org>,
	"oliver.upton@linux.dev" <oliver.upton@linux.dev>,
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	"maobibo@loongson.cn" <maobibo@loongson.cn>
Subject: Re: [PATCH v8 5/6] KVM: arm64: Allow cacheable stage 2 mapping using VMA flags
Date: Fri, 20 Jun 2025 13:07:11 +0000	[thread overview]
Message-ID: <SA1PR12MB7199F040DF62057947664992B07CA@SA1PR12MB7199.namprd12.prod.outlook.com> (raw)
In-Reply-To: <20250620122016.GD17127@nvidia.com>

>> -             s2_force_noncacheable = true;
>> +             bool cacheable_pfnmap = false;
>> +
>> +             if (vm_flags & VM_PFNMAP) {
>
> I think this same logic works equally well for MIXEDMAP. A cachable
> MIXEDMAP should follow the same rules for PFNMAP for the non-normal
> pages within it. IOW, just remove this if, it was already done above.

I see. Sure, I'll update to remove the check.


>> +                     /*
>> +                      * COW VM_PFNMAP is possible when doing a MAP_PRIVATE
>> +                      * /dev/mem mapping on systems that allow such mapping.
>> +                      * Reject such case.
>> +                      */
>
> This is where a COW mapping come from, but it doesn't explain why KVM
> has a problem here?

Actually I am not entirely sure of the reason. My read on that was that COW of
PFNMAP is a normal page backed by struct page that doesn't follow linearity.
Not sure if that conflicts with user_mem_abort() assumptions. Will need
David's take on that.

>> +                     if (is_vma_cacheable)
>> +                             cacheable_pfnmap = true;
>> +             }
>> +
>> +             if (cacheable_pfnmap) {
>
> If the vm_flags test is removed then this is just is_vma_cacheable

Thanks for catching that. We shouldn't need this variable.

>> +                      * ARM64 KVM relies on kernel VA mapping to the PFN to
>> +                      * perform cache maintenance as the CMO instructions work on
>> +                      * virtual addresses. VM_PFNMAP region are not necessarily
>> +                      * mapped to a KVA and hence the presence of hardware features
>> +                      * S2FWB and CACHE DIC is mandatory for cache maintenance.
>
> "are mandatory to avoid any cache maintenance"

Right, thanks.

> Jason

  reply	other threads:[~2025-06-20 13:07 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-20 12:09 [PATCH v8 0/6] KVM: arm64: Map GPU device memory as cacheable ankita
2025-06-20 12:09 ` [PATCH v8 1/6] KVM: arm64: Rename the device variable to s2_force_noncacheable ankita
2025-06-20 12:09 ` [PATCH v8 2/6] KVM: arm64: Update the check to detect device memory ankita
2025-06-20 12:09 ` [PATCH v8 3/6] KVM: arm64: Block cacheable PFNMAP mapping ankita
2025-06-20 12:09 ` [PATCH v8 4/6] KVM: arm64: New function to determine hardware cache management support ankita
2025-06-20 12:09 ` [PATCH v8 5/6] KVM: arm64: Allow cacheable stage 2 mapping using VMA flags ankita
2025-06-20 12:20   ` Jason Gunthorpe
2025-06-20 13:07     ` Ankit Agrawal [this message]
2025-06-20 12:09 ` [PATCH v8 6/6] KVM: arm64: Expose new KVM cap for cacheable PFNMAP ankita

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