From: Ankit Agrawal <ankita@nvidia.com>
To: Marc Zyngier <maz@kernel.org>
Cc: Jason Gunthorpe <jgg@nvidia.com>,
"oliver.upton@linux.dev" <oliver.upton@linux.dev>,
"joey.gouly@arm.com" <joey.gouly@arm.com>,
"suzuki.poulose@arm.com" <suzuki.poulose@arm.com>,
"yuzenghui@huawei.com" <yuzenghui@huawei.com>,
"catalin.marinas@arm.com" <catalin.marinas@arm.com>,
"will@kernel.org" <will@kernel.org>,
"ryan.roberts@arm.com" <ryan.roberts@arm.com>,
"shahuang@redhat.com" <shahuang@redhat.com>,
"lpieralisi@kernel.org" <lpieralisi@kernel.org>,
"david@redhat.com" <david@redhat.com>,
Aniket Agashe <aniketa@nvidia.com>, Neo Jia <cjia@nvidia.com>,
Kirti Wankhede <kwankhede@nvidia.com>,
"Tarun Gupta (SW-GPU)" <targupta@nvidia.com>,
Vikram Sethi <vsethi@nvidia.com>,
Andy Currid <acurrid@nvidia.com>,
Alistair Popple <apopple@nvidia.com>,
John Hubbard <jhubbard@nvidia.com>,
Dan Williams <danw@nvidia.com>, Zhi Wang <zhiw@nvidia.com>,
Matt Ochs <mochs@nvidia.com>, Uday Dhoke <udhoke@nvidia.com>,
Dheeraj Nigam <dnigam@nvidia.com>,
Krishnakant Jaju <kjaju@nvidia.com>,
"alex.williamson@redhat.com" <alex.williamson@redhat.com>,
"sebastianene@google.com" <sebastianene@google.com>,
"coltonlewis@google.com" <coltonlewis@google.com>,
"kevin.tian@intel.com" <kevin.tian@intel.com>,
"yi.l.liu@intel.com" <yi.l.liu@intel.com>,
"ardb@kernel.org" <ardb@kernel.org>,
"akpm@linux-foundation.org" <akpm@linux-foundation.org>,
"gshan@redhat.com" <gshan@redhat.com>,
"linux-mm@kvack.org" <linux-mm@kvack.org>,
"ddutile@redhat.com" <ddutile@redhat.com>,
"tabba@google.com" <tabba@google.com>,
"qperret@google.com" <qperret@google.com>,
"seanjc@google.com" <seanjc@google.com>,
"kvmarm@lists.linux.dev" <kvmarm@lists.linux.dev>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v3 1/1] KVM: arm64: Allow cacheable stage 2 mapping using VMA flags
Date: Mon, 17 Mar 2025 05:55:55 +0000 [thread overview]
Message-ID: <SA1PR12MB7199B320DAE42A8D7038A78EB0D32@SA1PR12MB7199.namprd12.prod.outlook.com> (raw)
In-Reply-To: <87tt7y7j6r.wl-maz@kernel.org>
>> For my education, what is an accepted way to communicate this? Please let
>> me know if there are any relevant examples that you may be aware of.
>
> A KVM capability is what is usually needed.
I see. If IIUC, this would involve a corresponding Qemu (usermode) change
to fetch the new KVM cap. Then it could fail in case the FWB is not
supported with some additional conditions (so that the currently supported
configs with !FWB won't break on usermode).
The proposed code change is to map in S2 as NORMAL when vma flags
has VM_PFNMAP. However, Qemu cannot know that driver is mapping
with PFNMAP or not. So how may Qemu decide whether it is okay to
fail for !FWB or not?
> This must be checked at the point of memslot creation, and return an
> error at that point. Memslots are all about stage-2, so it makes sense
> to check it there.
Ack, will add the check.
>
> M.
>
> --
> Without deviation from the norm, progress is not possible.
next prev parent reply other threads:[~2025-03-17 5:56 UTC|newest]
Thread overview: 61+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-10 10:30 [PATCH v3 0/1] KVM: arm64: Map GPU device memory as cacheable ankita
2025-03-10 10:30 ` [PATCH v3 1/1] KVM: arm64: Allow cacheable stage 2 mapping using VMA flags ankita
2025-03-10 11:54 ` Marc Zyngier
2025-03-11 3:42 ` Ankit Agrawal
2025-03-11 11:18 ` Marc Zyngier
2025-03-11 12:07 ` Ankit Agrawal
2025-03-12 8:21 ` Marc Zyngier
2025-03-17 5:55 ` Ankit Agrawal [this message]
2025-03-17 9:27 ` Marc Zyngier
2025-03-17 19:54 ` Catalin Marinas
2025-03-18 9:39 ` Marc Zyngier
2025-03-18 12:55 ` Jason Gunthorpe
2025-03-18 19:27 ` Catalin Marinas
2025-03-18 19:35 ` David Hildenbrand
2025-03-18 19:40 ` Oliver Upton
2025-03-20 3:30 ` bibo mao
2025-03-20 7:24 ` bibo mao
2025-03-18 23:17 ` Jason Gunthorpe
2025-03-19 18:03 ` Catalin Marinas
2025-03-18 19:30 ` Oliver Upton
2025-03-18 23:09 ` Jason Gunthorpe
2025-03-19 7:01 ` Oliver Upton
2025-03-19 17:04 ` Jason Gunthorpe
2025-03-19 18:11 ` Catalin Marinas
2025-03-19 19:22 ` Jason Gunthorpe
2025-03-19 21:48 ` Catalin Marinas
2025-03-26 8:31 ` Ankit Agrawal
2025-03-26 14:53 ` Sean Christopherson
2025-03-26 15:42 ` Marc Zyngier
2025-03-26 16:10 ` Sean Christopherson
2025-03-26 18:02 ` Marc Zyngier
2025-03-26 18:24 ` Sean Christopherson
2025-03-26 18:51 ` Oliver Upton
2025-03-31 14:44 ` Jason Gunthorpe
2025-03-31 14:56 ` Jason Gunthorpe
2025-04-07 15:20 ` Sean Christopherson
2025-04-07 16:15 ` Jason Gunthorpe
2025-04-07 16:43 ` Sean Christopherson
2025-04-16 8:51 ` Ankit Agrawal
2025-04-21 16:03 ` Ankit Agrawal
2025-04-22 7:49 ` Oliver Upton
2025-04-22 13:54 ` Jason Gunthorpe
2025-04-22 16:50 ` Catalin Marinas
2025-04-22 17:03 ` Jason Gunthorpe
2025-04-22 21:28 ` Oliver Upton
2025-04-22 23:35 ` Jason Gunthorpe
2025-04-23 10:45 ` Catalin Marinas
2025-04-23 12:02 ` Jason Gunthorpe
2025-04-23 12:26 ` Catalin Marinas
2025-04-23 13:03 ` Jason Gunthorpe
2025-04-29 10:47 ` Ankit Agrawal
2025-04-29 13:27 ` Catalin Marinas
2025-04-29 14:14 ` Jason Gunthorpe
2025-04-29 16:03 ` Catalin Marinas
2025-04-29 16:44 ` Jason Gunthorpe
2025-04-29 18:09 ` Catalin Marinas
2025-04-29 18:19 ` Jason Gunthorpe
2025-05-07 15:26 ` Ankit Agrawal
2025-05-09 12:47 ` Catalin Marinas
2025-04-22 14:53 ` Sean Christopherson
2025-03-18 12:57 ` Jason Gunthorpe
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=SA1PR12MB7199B320DAE42A8D7038A78EB0D32@SA1PR12MB7199.namprd12.prod.outlook.com \
--to=ankita@nvidia.com \
--cc=acurrid@nvidia.com \
--cc=akpm@linux-foundation.org \
--cc=alex.williamson@redhat.com \
--cc=aniketa@nvidia.com \
--cc=apopple@nvidia.com \
--cc=ardb@kernel.org \
--cc=catalin.marinas@arm.com \
--cc=cjia@nvidia.com \
--cc=coltonlewis@google.com \
--cc=danw@nvidia.com \
--cc=david@redhat.com \
--cc=ddutile@redhat.com \
--cc=dnigam@nvidia.com \
--cc=gshan@redhat.com \
--cc=jgg@nvidia.com \
--cc=jhubbard@nvidia.com \
--cc=joey.gouly@arm.com \
--cc=kevin.tian@intel.com \
--cc=kjaju@nvidia.com \
--cc=kvmarm@lists.linux.dev \
--cc=kwankhede@nvidia.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mm@kvack.org \
--cc=lpieralisi@kernel.org \
--cc=maz@kernel.org \
--cc=mochs@nvidia.com \
--cc=oliver.upton@linux.dev \
--cc=qperret@google.com \
--cc=ryan.roberts@arm.com \
--cc=seanjc@google.com \
--cc=sebastianene@google.com \
--cc=shahuang@redhat.com \
--cc=suzuki.poulose@arm.com \
--cc=tabba@google.com \
--cc=targupta@nvidia.com \
--cc=udhoke@nvidia.com \
--cc=vsethi@nvidia.com \
--cc=will@kernel.org \
--cc=yi.l.liu@intel.com \
--cc=yuzenghui@huawei.com \
--cc=zhiw@nvidia.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox