From mboxrd@z Thu Jan 1 00:00:00 1970 Date: Fri, 14 Jan 2005 09:08:54 -0800 (PST) From: Christoph Lameter Subject: Re: page table lock patch V15 [0/7]: overview In-Reply-To: <20050114170140.GB4634@muc.de> Message-ID: References: <41E5B7AD.40304@yahoo.com.au> <41E5BC60.3090309@yahoo.com.au> <20050113031807.GA97340@muc.de> <20050113180205.GA17600@muc.de> <20050114043944.GB41559@muc.de> <20050114170140.GB4634@muc.de> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Sender: owner-linux-mm@kvack.org Return-Path: To: Andi Kleen Cc: Nick Piggin , Andrew Morton , torvalds@osdl.org, hugh@veritas.com, linux-mm@kvack.org, linux-ia64@vger.kernel.org, linux-kernel@vger.kernel.org, benh@kernel.crashing.org List-ID: On Fri, 14 Jan 2005, Andi Kleen wrote: > > Looked at arch/i386/lib/mmx.c. It avoids the mmx ops in an interrupt > > context but the rest of the prep for mmx only saves the fpu state if its > > in use. So that code would only be used rarely. The mmx 64 bit > > instructions seem to be quite fast according to the manual. Double the > > cycles than the 32 bit instructions on Pentium M (somewhat higher on Pentium 4). > > With all the other overhead (disabling exceptions, saving register etc.) > will be likely slower. Also you would need fallback paths for CPUs > without MMX but with PAE (like Ppro). You can benchmark > it if you want, but I wouldn't be very optimistic. So the PentiumPro is a cpu with atomic 64 bit operations in a cmpxchg but no instruction to do an atomic 64 bit store or load although the architecture conceptually supports 64bit atomic stores and loads? Wild. -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: aart@kvack.org