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Sun, 09 Feb 2025 23:30:20 -0800 (PST) MIME-Version: 1.0 References: <20250206044346.3810242-1-riel@surriel.com> <20250206044346.3810242-5-riel@surriel.com> In-Reply-To: <20250206044346.3810242-5-riel@surriel.com> From: Vern Hao Date: Mon, 10 Feb 2025 15:30:09 +0800 X-Gm-Features: AWEUYZmwVLmAKHIHsgs_PPO_iym3SCGRWLU7t06clsyWCBeh_7LXaSvEaD_m0H8 Message-ID: Subject: Re: [PATCH v9 04/12] x86/mm: get INVLPGB count max from CPUID To: Rik van Riel Cc: x86@kernel.org, linux-kernel@vger.kernel.org, bp@alien8.de, peterz@infradead.org, dave.hansen@linux.intel.com, zhengqi.arch@bytedance.com, nadav.amit@gmail.com, thomas.lendacky@amd.com, kernel-team@meta.com, linux-mm@kvack.org, akpm@linux-foundation.org, jannh@google.com, mhklinux@outlook.com, andrew.cooper3@citrix.com, Manali Shukla Content-Type: multipart/alternative; boundary="0000000000003c856f062dc4ae5d" X-Rspamd-Queue-Id: 877E61C0003 X-Stat-Signature: 9robg9zrpzy7u1aznwbhp9a9tcgxb589 X-Rspam-User: X-Rspamd-Server: rspam01 X-HE-Tag: 1739172621-20202 X-HE-Meta: U2FsdGVkX1/VkyQluEg6B6dHnQZvDXEUkJFfQQ9LeA0p94AEFdVuUJrECBrdPAlXVuJWmJ7rkM452dHw44mQRuCYkL0TqQCCgOQmhYgkn0epGoWKEwwGhKe3Iz8VdZqrDkYWtYfyT3OcLeT7RdQn8Z3Ye0bnxOWYQv51lmS1jH0tU2JyYKav9pzuGFvEP+B3gf9ST7o7BP7QVNAiegCdboVixfaQDaf5XvKtixw1p9HjqxPA32V0enP0ndNw/HTpmX8ntMb6ogxBT9NjsOwVd8w7mPjVSyg8sAV8NVmfayR82HzJ9VWU1man6OYNRTiTCXL1nMiiLTYIHaVT27fRqTzTGlzanG78etxbXeBHX2QuaSOllG/5jVE531JUY3EzX7pjDfbSsJEDI3uS/oudAr+ySXZaMNxLpjQCuriBR1zmhuLx1KPAhcFdXXieVQxgmo1rQPdP+pAYKmUFHuWhc+BoUm0EhE9Ha5ln8+L7GpjsyLg11jhHxehieJMkjHLeb+C819J8s8KDAaP+PAVRoiEuOy01WGWwuX2umUIGcqvk6cZIP71Y7nGIVNz9M27Xdvu2+pztv2iHaPStDunQG2DvmhRkR6SbNMiXs96d/conlluC9asSidcRqjAyq9GDRTyFjMbmKhYon+hnKzv1HgHSVAf/a6MMzCt1/1SVhhZHxkEVB6Mitt4iMfjb+XazR6m6fCK2UJrOJy5wLQXwNlCWRd6oqpFlTd801q7FmmWr8ikvg30oIcocUeOimX+HCffpqP7etQfWHW+wtELsxdjLgYyn/Zl3ZGiYmIIX/mC0U8JTIkhi6W4qtLIyPffUPei4bdXFILsHv0iv1IuIS//+jvNivaCZPW/q2LdpBqJSOX+8+awY5eAZzk2iY/9+s4JoSvH6jA60Gtly2Cx9eZriJSjUGTpKe6t+ARCQN3DUbcrURXlTHYg7MQWRG/bgNh0CtH0TD2rax+i2/F1 e3CL8Vsp MGRRIbTovCp0xeKiRdjW4R1kfRsgX+ih8mNEJCSb7+KpoyOL0r/Wf6tCFqjUU24IahhT2SFwHa4wRhCNZ6M3zTChHZAzfWZ66Wd8l8HqNyAg/wjugp+awFwEsDD9n8gfzKBxRpQJbSzm/YjXjUBuo6EbwhftEEy6FgZ1S8clCyRxIrUIvCJz5NiE2EdMtBEtWJH3C4OPZfjhEnKUsvcCRX1bAQ1qJ3LgjflESZtG3JEfFXbcwnspswMKlJxWB+QG6O1saLRZ/cApJ7UTlxlrhhuVo/xI0xATTTl4Q+uf6x/PRcw+nBCSBagHRFpZ+QKm3yu+5Y2j6KD89pxTnGYMSQru5kt0yFTwb1qcTYYDfp/qnlm70oJgWoe8XUSJkj+H5oofC68BbCs0Jx7UAWNUUp4uHj2x6+ZV0+NVPXEFc9iubtDvyj5bPjaU25cP0vhw6cDB+D2eg5GlYbmUFPa6hMMVlsftbekBoXSQiESKQQO2+6yMoLMoX/mxeC7cCG5QNDipTZoMe2XK8nosrW1G3eoB9dPGMi/36p56cBsTobrpmI6H0PSeDm6R593VM1GP8CiPH6qIH2o3/wYs= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: --0000000000003c856f062dc4ae5d Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable *I do some test on my Machine with AMD EPYC 7K83, these patches work on my host, but failed on my guest with qemu.* *in host, use lscpu cmd, you can see invlpgb in flags, but in guest no.* *So are you plan to support it in guest?* Best Regards! Thanks Rik van Riel =E4=BA=8E2025=E5=B9=B42=E6=9C=886=E6=97=A5= =E5=91=A8=E5=9B=9B 12:45=E5=86=99=E9=81=93=EF=BC=9A > The CPU advertises the maximum number of pages that can be shot down > with one INVLPGB instruction in the CPUID data. > > Save that information for later use. > > Signed-off-by: Rik van Riel > Tested-by: Manali Shukla > --- > arch/x86/Kconfig.cpu | 5 +++++ > arch/x86/include/asm/cpufeatures.h | 1 + > arch/x86/include/asm/tlbflush.h | 7 +++++++ > arch/x86/kernel/cpu/amd.c | 8 ++++++++ > 4 files changed, 21 insertions(+) > > diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu > index 2a7279d80460..abe013a1b076 100644 > --- a/arch/x86/Kconfig.cpu > +++ b/arch/x86/Kconfig.cpu > @@ -395,6 +395,10 @@ config X86_VMX_FEATURE_NAMES > def_bool y > depends on IA32_FEAT_CTL > > +config X86_BROADCAST_TLB_FLUSH > + def_bool y > + depends on CPU_SUP_AMD && 64BIT > + > menuconfig PROCESSOR_SELECT > bool "Supported processor vendors" if EXPERT > help > @@ -431,6 +435,7 @@ config CPU_SUP_CYRIX_32 > config CPU_SUP_AMD > default y > bool "Support AMD processors" if PROCESSOR_SELECT > + select X86_BROADCAST_TLB_FLUSH > help > This enables detection, tunings and quirks for AMD processors > > diff --git a/arch/x86/include/asm/cpufeatures.h > b/arch/x86/include/asm/cpufeatures.h > index 17b6590748c0..f9b832e971c5 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -338,6 +338,7 @@ > #define X86_FEATURE_CLZERO (13*32+ 0) /* "clzero" CLZERO > instruction */ > #define X86_FEATURE_IRPERF (13*32+ 1) /* "irperf" > Instructions Retired Count */ > #define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* "xsaveerptr" Always > save/restore FP error pointers */ > +#define X86_FEATURE_INVLPGB (13*32+ 3) /* INVLPGB and TLBSYNC > instruction supported. */ > #define X86_FEATURE_RDPRU (13*32+ 4) /* "rdpru" Read > processor register at user level */ > #define X86_FEATURE_WBNOINVD (13*32+ 9) /* "wbnoinvd" WBNOINVD > instruction */ > #define X86_FEATURE_AMD_IBPB (13*32+12) /* Indirect Branch > Prediction Barrier */ > diff --git a/arch/x86/include/asm/tlbflush.h > b/arch/x86/include/asm/tlbflush.h > index 02fc2aa06e9e..8fe3b2dda507 100644 > --- a/arch/x86/include/asm/tlbflush.h > +++ b/arch/x86/include/asm/tlbflush.h > @@ -183,6 +183,13 @@ static inline void cr4_init_shadow(void) > extern unsigned long mmu_cr4_features; > extern u32 *trampoline_cr4_features; > > +/* How many pages can we invalidate with one INVLPGB. */ > +#ifdef CONFIG_X86_BROADCAST_TLB_FLUSH > +extern u16 invlpgb_count_max; > +#else > +#define invlpgb_count_max 1 > +#endif > + > extern void initialize_tlbstate_and_flush(void); > > /* > diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c > index 79d2e17f6582..bcf73775b4f8 100644 > --- a/arch/x86/kernel/cpu/amd.c > +++ b/arch/x86/kernel/cpu/amd.c > @@ -29,6 +29,8 @@ > > #include "cpu.h" > > +u16 invlpgb_count_max __ro_after_init; > + > static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) > { > u32 gprs[8] =3D { 0 }; > @@ -1135,6 +1137,12 @@ static void cpu_detect_tlb_amd(struct cpuinfo_x86 > *c) > tlb_lli_2m[ENTRIES] =3D eax & mask; > > tlb_lli_4m[ENTRIES] =3D tlb_lli_2m[ENTRIES] >> 1; > + > + /* Max number of pages INVLPGB can invalidate in one shot */ > + if (boot_cpu_has(X86_FEATURE_INVLPGB)) { > + cpuid(0x80000008, &eax, &ebx, &ecx, &edx); > + invlpgb_count_max =3D (edx & 0xffff) + 1; > + } > } > > static const struct cpu_dev amd_cpu_dev =3D { > -- > 2.47.1 > > > --0000000000003c856f062dc4ae5d Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
I do some test=C2=A0on my=C2=A0=C2= =A0Machine with=C2=A0AMD EPYC 7K83,=C2=A0 these patches=C2=A0work on= my host,=C2=A0 but failed on my guest=C2=A0with qemu.<= /div>

in host, use lscpu = cmd, you can see=C2=A0=C2=A0invlpgb=C2=A0in flags,=C2=A0 but in guest no.

So ar= e you plan=C2=A0to support it in guest?

<= br>
Best Regards!
Thanks


Rik van Riel <riel@surriel.com> =E4=BA=8E2025=E5=B9=B42=E6=9C=886=E6=97= =A5=E5=91=A8=E5=9B=9B 12:45=E5=86=99=E9=81=93=EF=BC=9A
The CPU advertises the maximum numbe= r of pages that can be shot down
with one INVLPGB instruction in the CPUID data.

Save that information for later use.

Signed-off-by: Rik van Riel <riel@surriel.com>
Tested-by: Manali Shukla <Manali.Shukla@amd.com>
---
=C2=A0arch/x86/Kconfig.cpu=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0| 5 +++++
=C2=A0arch/x86/include/asm/cpufeatures.h | 1 +
=C2=A0arch/x86/include/asm/tlbflush.h=C2=A0 =C2=A0 | 7 +++++++
=C2=A0arch/x86/kernel/cpu/amd.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | 8 +++++= +++
=C2=A04 files changed, 21 insertions(+)

diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu
index 2a7279d80460..abe013a1b076 100644
--- a/arch/x86/Kconfig.cpu
+++ b/arch/x86/Kconfig.cpu
@@ -395,6 +395,10 @@ config X86_VMX_FEATURE_NAMES
=C2=A0 =C2=A0 =C2=A0 =C2=A0 def_bool y
=C2=A0 =C2=A0 =C2=A0 =C2=A0 depends on IA32_FEAT_CTL

+config X86_BROADCAST_TLB_FLUSH
+=C2=A0 =C2=A0 =C2=A0 =C2=A0def_bool y
+=C2=A0 =C2=A0 =C2=A0 =C2=A0depends on CPU_SUP_AMD && 64BIT
+
=C2=A0menuconfig PROCESSOR_SELECT
=C2=A0 =C2=A0 =C2=A0 =C2=A0 bool "Supported processor vendors" if= EXPERT
=C2=A0 =C2=A0 =C2=A0 =C2=A0 help
@@ -431,6 +435,7 @@ config CPU_SUP_CYRIX_32
=C2=A0config CPU_SUP_AMD
=C2=A0 =C2=A0 =C2=A0 =C2=A0 default y
=C2=A0 =C2=A0 =C2=A0 =C2=A0 bool "Support AMD processors" if PROC= ESSOR_SELECT
+=C2=A0 =C2=A0 =C2=A0 =C2=A0select X86_BROADCAST_TLB_FLUSH
=C2=A0 =C2=A0 =C2=A0 =C2=A0 help
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 This enables detection, tunings and quir= ks for AMD processors

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h
index 17b6590748c0..f9b832e971c5 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -338,6 +338,7 @@
=C2=A0#define X86_FEATURE_CLZERO=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0(13*32+ 0) /* "clzero" CLZERO instruction */
=C2=A0#define X86_FEATURE_IRPERF=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0(13*32+ 1) /* "irperf" Instructions Retired Count */
=C2=A0#define X86_FEATURE_XSAVEERPTR=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(13*3= 2+ 2) /* "xsaveerptr" Always save/restore FP error pointers */ +#define X86_FEATURE_INVLPGB=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (13*3= 2+ 3) /* INVLPGB and TLBSYNC instruction supported. */
=C2=A0#define X86_FEATURE_RDPRU=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 (13*32+ 4) /* "rdpru" Read processor register at user leve= l */
=C2=A0#define X86_FEATURE_WBNOINVD=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= (13*32+ 9) /* "wbnoinvd" WBNOINVD instruction */
=C2=A0#define X86_FEATURE_AMD_IBPB=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= (13*32+12) /* Indirect Branch Prediction Barrier */
diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflus= h.h
index 02fc2aa06e9e..8fe3b2dda507 100644
--- a/arch/x86/include/asm/tlbflush.h
+++ b/arch/x86/include/asm/tlbflush.h
@@ -183,6 +183,13 @@ static inline void cr4_init_shadow(void)
=C2=A0extern unsigned long mmu_cr4_features;
=C2=A0extern u32 *trampoline_cr4_features;

+/* How many pages can we invalidate with one INVLPGB. */
+#ifdef CONFIG_X86_BROADCAST_TLB_FLUSH
+extern u16 invlpgb_count_max;
+#else
+#define invlpgb_count_max 1
+#endif
+
=C2=A0extern void initialize_tlbstate_and_flush(void);

=C2=A0/*
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 79d2e17f6582..bcf73775b4f8 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -29,6 +29,8 @@

=C2=A0#include "cpu.h"

+u16 invlpgb_count_max __ro_after_init;
+
=C2=A0static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p= )
=C2=A0{
=C2=A0 =C2=A0 =C2=A0 =C2=A0 u32 gprs[8] =3D { 0 };
@@ -1135,6 +1137,12 @@ static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c= )
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 tlb_lli_2m[ENTRIES]= =3D eax & mask;

=C2=A0 =C2=A0 =C2=A0 =C2=A0 tlb_lli_4m[ENTRIES] =3D tlb_lli_2m[ENTRIES] >= ;> 1;
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0/* Max number of pages INVLPGB can invalidate i= n one shot */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0if (boot_cpu_has(X86_FEATURE_INVLPGB)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0cpuid(0x80000008, &= amp;eax, &ebx, &ecx, &edx);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0invlpgb_count_max = =3D (edx & 0xffff) + 1;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0}
=C2=A0}

=C2=A0static const struct cpu_dev amd_cpu_dev =3D {
--
2.47.1


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