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AJvYcCXq47AH5AK7D45D1J2OFhycZDvUwsjg1qCw/db/Shpv7+ioaLr9aZMxB+xpo3X66xh30mV29D0MeA==@kvack.org X-Gm-Message-State: AOJu0YwJsHXKEvM/4WdyudBuxQ/xoNvCej8acbiWtrcJOM6bjVmWfrKr KEg6EugnOznqQp421+/CRmRrKazb9vMCCUXyyHxadlyoiMPp5rIticSpNUJ3CDaZ3ZDOVu56VNw DDYJA/ChS8brL/naattT9hNlXlF7WuOZuf1y5/qgJUqqdQ5aW/E4MRg== X-Gm-Gg: ASbGncvFR6ZBv219Ju4IEQcqzE8ZaPEGFWQFK6tLmPxVSHfbbb7RIJYQGhhE0lSPuTn SEvFLxsUQjhT6qp4zYb6jjt+TI9IVQ3wgilR0mWhcOs14F95J X-Google-Smtp-Source: AGHT+IEUYjjxoNVonXftGirFN2eYx0YoHUjkucusrRhp2lBZDnBg/ur7q7d/l8gQ0l23mUaXrY71JWBrqUptthTQgSA= X-Received: by 2002:a17:90b:2ccd:b0:2ee:45fd:34ee with SMTP id 98e67ed59e1d1-2ef6ab29c3emr2272187a91.37.1733452899670; Thu, 05 Dec 2024 18:41:39 -0800 (PST) MIME-Version: 1.0 References: <20241205103729.14798-1-luxu.kernel@bytedance.com> In-Reply-To: From: Xu Lu Date: Fri, 6 Dec 2024 10:41:28 +0800 Message-ID: Subject: Re: [External] Re: [RFC PATCH v2 00/21] riscv: Introduce 64K base page To: Zi Yan Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, ardb@kernel.org, anup@brainfault.org, atishp@atishpatra.org, xieyongji@bytedance.com, lihangjing@bytedance.com, punit.agrawal@bytedance.com, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Linux MM Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Rspam-User: X-Rspamd-Server: rspam03 X-Rspamd-Queue-Id: 5CDC2160008 X-Stat-Signature: n3g97utgfud7nd8m1ijawq7m18yckkjh X-HE-Tag: 1733452890-499474 X-HE-Meta: U2FsdGVkX1+/kXDDAa7S+KJUC9w3u+evuPoOcWaiZuPaOLltLfNmr/4ZE5hkB0lgU3Fyp08xDnlDULNBkcmErCJvEWLe2VYbxVQo4R4qQXC4Acug7u1Z4a+fImioVyuHW+w7iRGfVbZF09oFWjwU4AkH1Ac23Q6PEOjis9tKlg1W/Pnt6ps1GKfwkiTUGtM9rrEKlqnmBpH4VyjQdPgT4VqddEIMxrkHAlC0Eez1Fl7A8vG3job9VuuRP0DKbv0B+LEjdDAqUUKR4Dlm/CT4xTABc+udHlJA5UO4/c1cgDJ7MdQ99zzrAzXdaDkyWfhFU2Nh3ep8BNCBVcGvFaDVnU5/JR0CuTc4UM5glNFkBuMemmipsujR8+mex9+ozM7bQ+FB5Jml9lY2V4R2leH8OVA5Ky39wJbZPtRmwkM1hSphLMwP82uf7bQKX1kEjqNMYMxx/vMcYmIWlpEDJMjCs5DoCnaLf3/SDhb6whyjUDPMIrqn2AK/EgSxZKeOyLjnNm6msIuoNM5gBehJhcDVwIGF7f/pO0XiZ2+Rq+EOdSbGTgyhS+D+aePuLu8XxMm7lHTkzRVv7c2hW2Nc4JYy6f9bfrqFTC7jn8SHpF8UXFkhwfMCZ1LXb514jQF4W3/2YdnKxwwOpLoae1Nf3PHsKgv3tD+aYjOc5Ed4EjfBwN+Fc0vJf64/CDfYPH9baGxT2lDw0KrmnG1BDyj4thK98PQvFLxf9KlOqD4xS4AwGCLLVQ4npR0wIgb1xSmm1KZ2+FQYHuVgO3nDdAap3jRE2J9cBkmQhnIjqj605AY0st+6hyR/oIkdgz6MjYibi4H7ajWMaSCYBCBBuEXfD/pFs3+VCSgRv+Tu/8njpDIU4WJwiGq/rpINYWlc/6nphigOf2Mv5gIMyb3VfwCdyAQJFFH8jmwRuKcDcTRJJJn7HYntwbdt6TlUr4pUaz+/SFuGUCSA1g+ESJ98CzBJu97 ikPcGgfv Htmxza1d9Rj0oGSIckeigry+AgS23o08LLmRGIaSytby84KYLlMj9c/hiWbmY1SJCmw7v5cxt0rSpWA8ZarPRAPYw+IVH3N1Rh5G/+6HP7Ewc5tza90cAKRSffO7bcvtH5hZGeQ4siT0k8UgmUv0iJk1xvPhTc/ZhKZp6JzayoJWSbeVY6fotowV8e11GMkh/MCqO2IHJI0ClzeyEuza8pr+t9R4UJOMdjiMedLa6z+iEP9KRrlT6zvnHhTHb382I6eOpozeO45J5cMZjPWZLa1Y07iuRIuNmnnV7GSYyQxwR/EtIX64zuQi1DDIR3/eqD6aGt548zM1ouw+YdaGJQLvrvyYfs5g5XDA/ X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Hi Zi Yan, On Fri, Dec 6, 2024 at 10:00=E2=80=AFAM Zi Yan wrote: > > On 5 Dec 2024, at 5:37, Xu Lu wrote: > > > This patch series attempts to break through the limitation of MMU and > > supports larger base page on RISC-V, which only supports 4K page size > > now. The key idea is to always manage and allocate memory at a > > granularity of 64K and use SVNAPOT to accelerate address translation. > > This is the second version and the detailed introduction can be found > > in [1]. > > > > Changes from v1: > > - Rebase on v6.12. > > > > - Adjust the page table entry shift to reduce page table memory usage. > > For example, in SV39, the traditional va behaves as: > > > > ---------------------------------------------- > > | pgd index | pmd index | pte index | offset | > > ---------------------------------------------- > > | 38 30 | 29 21 | 20 12 | 11 0 | > > ---------------------------------------------- > > > > When we choose 64K as basic software page, va now behaves as: > > > > ---------------------------------------------- > > | pgd index | pmd index | pte index | offset | > > ---------------------------------------------- > > | 38 34 | 33 25 | 24 16 | 15 0 | > > ---------------------------------------------- > > > > - Fix some bugs in v1. > > > > Thanks in advance for comments. > > > > [1] https://lwn.net/Articles/952722/ > > This looks very interesting. Can you cc me and linux-mm@kvack.org > in the future? Thanks. Of course. Hope this patch can be of any help. > > Have you thought about doing it for ARM64 4KB as well? ARM64=E2=80=99s co= ntig PTE > should have similar effect of RISC-V=E2=80=99s SVNAPOT, right? I have not thought about it yet. ARM64 has native 64K MMU. The kernel can directly configure the page size as 64K and MMU will do translation at corresponding granularity. So I doubt if there is a need to implement 64K Page Size based on CONT PTE. If you want to use CONT PTE for acceleration instead of 64K MMU, maybe you can have a try on THP_CONTPTE[1] which has been merged~ [1] https://lwn.net/Articles/935887/ Best regards, Xu Lu > > > > > Xu Lu (21): > > riscv: mm: Distinguish hardware base page and software base page > > riscv: mm: Configure satp with hw page pfn > > riscv: mm: Reimplement page table entry structures > > riscv: mm: Reimplement page table entry constructor function > > riscv: mm: Reimplement conversion functions between page table entry > > riscv: mm: Avoid pte constructor during pte conversion > > riscv: mm: Reimplement page table entry get function > > riscv: mm: Reimplement page table entry atomic get function > > riscv: mm: Replace READ_ONCE with atomic pte get function > > riscv: mm: Reimplement PTE A/D bit check function > > riscv: mm: Reimplement mk_huge_pte function > > riscv: mm: Reimplement tlb flush function > > riscv: mm: Adjust PGDIR/P4D/PUD/PMD_SHIFT > > riscv: mm: Only apply svnapot region bigger than software page > > riscv: mm: Adjust FIX_BTMAPS_SLOTS for variable PAGE_SIZE > > riscv: mm: Adjust FIX_FDT_SIZE for variable PMD_SIZE > > riscv: mm: Apply Svnapot for base page mapping if possible > > riscv: Kconfig: Introduce 64K page size > > riscv: Kconfig: Adjust mmap rnd bits for 64K Page > > riscv: mm: Adjust address space layout and init page table for 64K > > Page > > riscv: mm: Update EXEC_PAGESIZE for 64K Page > > > > arch/riscv/Kconfig | 34 +- > > arch/riscv/include/asm/fixmap.h | 3 +- > > arch/riscv/include/asm/hugetlb.h | 5 + > > arch/riscv/include/asm/page.h | 56 ++- > > arch/riscv/include/asm/pgtable-32.h | 12 +- > > arch/riscv/include/asm/pgtable-64.h | 128 ++++-- > > arch/riscv/include/asm/pgtable-bits.h | 3 +- > > arch/riscv/include/asm/pgtable.h | 564 +++++++++++++++++++++++--- > > arch/riscv/include/asm/tlbflush.h | 26 +- > > arch/riscv/include/uapi/asm/param.h | 24 ++ > > arch/riscv/kernel/head.S | 4 +- > > arch/riscv/kernel/hibernate.c | 21 +- > > arch/riscv/mm/context.c | 7 +- > > arch/riscv/mm/fault.c | 15 +- > > arch/riscv/mm/hugetlbpage.c | 30 +- > > arch/riscv/mm/init.c | 45 +- > > arch/riscv/mm/kasan_init.c | 7 +- > > arch/riscv/mm/pgtable.c | 111 ++++- > > arch/riscv/mm/tlbflush.c | 31 +- > > arch/s390/include/asm/hugetlb.h | 2 +- > > include/asm-generic/hugetlb.h | 5 +- > > include/linux/pgtable.h | 21 + > > kernel/events/core.c | 6 +- > > mm/debug_vm_pgtable.c | 6 +- > > mm/gup.c | 10 +- > > mm/hmm.c | 2 +- > > mm/hugetlb.c | 4 +- > > mm/mapping_dirty_helpers.c | 2 +- > > mm/memory.c | 4 +- > > mm/mprotect.c | 2 +- > > mm/ptdump.c | 8 +- > > mm/sparse-vmemmap.c | 2 +- > > mm/vmscan.c | 2 +- > > 33 files changed, 1029 insertions(+), 173 deletions(-) > > create mode 100644 arch/riscv/include/uapi/asm/param.h > > > > -- > > 2.20.1 > > > Best Regards, > Yan, Zi