From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pb0-f45.google.com (mail-pb0-f45.google.com [209.85.160.45]) by kanga.kvack.org (Postfix) with ESMTP id 6409F6B0174 for ; Thu, 7 Nov 2013 14:59:53 -0500 (EST) Received: by mail-pb0-f45.google.com with SMTP id ma3so1074708pbc.18 for ; Thu, 07 Nov 2013 11:59:53 -0800 (PST) Received: from psmtp.com ([74.125.245.147]) by mx.google.com with SMTP id cj2si3738722pbc.57.2013.11.07.11.59.51 for ; Thu, 07 Nov 2013 11:59:52 -0800 (PST) Received: by mail-qc0-f171.google.com with SMTP id i7so867116qcq.2 for ; Thu, 07 Nov 2013 11:59:49 -0800 (PST) MIME-Version: 1.0 In-Reply-To: <20131107143139.GT18245@linux.vnet.ibm.com> References: <1383773827.11046.355.camel@schen9-DESK> <20131107143139.GT18245@linux.vnet.ibm.com> Date: Thu, 7 Nov 2013 11:59:49 -0800 Message-ID: Subject: Re: [PATCH v3 3/5] MCS Lock: Barrier corrections From: Michel Lespinasse Content-Type: text/plain; charset=ISO-8859-1 Sender: owner-linux-mm@kvack.org List-ID: To: Paul McKenney Cc: Linus Torvalds , Waiman Long , Arnd Bergmann , Rik van Riel , Aswin Chandramouleeswaran , Raghavendra K T , "Figo. zhang" , linux-arch@vger.kernel.org, Andi Kleen , Peter Zijlstra , George Spelvin , Tim Chen , Ingo Molnar , Peter Hurley , "H. Peter Anvin" , Andrew Morton , linux-mm , Andrea Arcangeli , Alex Shi , LKML , Scott J Norton , Thomas Gleixner , Dave Hansen , Matthew R Wilcox , Will Deacon , Davidlohr Bueso On Thu, Nov 7, 2013 at 6:31 AM, Paul E. McKenney wrote: > On Thu, Nov 07, 2013 at 04:50:23AM -0800, Michel Lespinasse wrote: >> On Thu, Nov 7, 2013 at 4:06 AM, Linus Torvalds >> wrote: >> > >> > On Nov 7, 2013 6:55 PM, "Michel Lespinasse" wrote: >> >> >> >> Rather than writing arch-specific locking code, would you agree to >> >> introduce acquire and release memory operations ? >> > >> > Yes, that's probably the right thing to do. What ops do we need? Store with >> > release, cmpxchg and load with acquire? Anything else? >> >> Depends on what lock types we want to implement on top; for MCS we would need: >> - xchg acquire (common case) and load acquire (for spinning on our >> locker's wait word) >> - cmpxchg release (when there is no next locker) and store release >> (when writing to the next locker's wait word) >> >> One downside of the proposal is that using a load acquire for spinning >> puts the memory barrier within the spin loop. So this model is very >> intuitive and does not add unnecessary barriers on x86, but it my >> place the barriers in a suboptimal place for architectures that need >> them. > > OK, I will bite... Why is a barrier in the spinloop suboptimal? It's probably not a big deal - all I meant to say is that if you were manually placing barriers, you would probably put one after the loop instead. I don't deal much with architectures where such barriers are needed, so I don't know for sure if the difference means much. > Can't say that I have tried measuring it, but the barrier should not > normally result in interconnect traffic. Given that the barrier is > required anyway, it should not affect lock-acquisition latency. Agree > So what am I missing here? I think you read my second email as me trying to shoot down a proposal - I wasn't, as I really like the acquire/release model and find it easy to program with, which is why I'm proposing it in the first place. I just wanted to be upfront about all potential downsides, so we can consider them and see if they are significant - I don't think they are, but I'm not the best person to judge that as I mostly just deal with x86 stuff. -- Michel "Walken" Lespinasse A program is never fully debugged until the last user dies. -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org