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[209.85.128.178]) by smtp.gmail.com with ESMTPSA id i12-20020a05620a150c00b007402fdda195sm4948334qkk.123.2023.02.27.06.43.21 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 27 Feb 2023 06:43:22 -0800 (PST) Received: by mail-yw1-f178.google.com with SMTP id 00721157ae682-536b7ffdd34so181718057b3.6 for ; Mon, 27 Feb 2023 06:43:21 -0800 (PST) X-Received: by 2002:a81:ad43:0:b0:533:91d2:9d94 with SMTP id l3-20020a81ad43000000b0053391d29d94mr10571733ywk.5.1677509001567; Mon, 27 Feb 2023 06:43:21 -0800 (PST) MIME-Version: 1.0 References: <20230113171026.582290-1-david@redhat.com> <20230113171026.582290-12-david@redhat.com> <9ed766a6-cf06-535d-3337-ea6ff25c2362@redhat.com> In-Reply-To: <9ed766a6-cf06-535d-3337-ea6ff25c2362@redhat.com> From: Geert Uytterhoeven Date: Mon, 27 Feb 2023 15:43:07 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH mm-unstable v1 11/26] microblaze/mm: support __HAVE_ARCH_PTE_SWP_EXCLUSIVE To: David Hildenbrand Cc: linux-kernel@vger.kernel.org, Andrew Morton , Hugh Dickins , John Hubbard , Jason Gunthorpe , Mike Rapoport , Yang Shi , Vlastimil Babka , Nadav Amit , Andrea Arcangeli , Peter Xu , linux-mm@kvack.org, x86@kernel.org, linux-alpha@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-csky@vger.kernel.org, linux-hexagon@vger.kernel.org, linux-ia64@vger.kernel.org, loongarch@lists.linux.dev, linux-m68k@lists.linux-m68k.org, linux-mips@vger.kernel.org, openrisc@lists.librecores.org, linux-parisc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-riscv@lists.infradead.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-um@lists.infradead.org, linux-xtensa@linux-xtensa.org, Michal Simek Content-Type: text/plain; charset="UTF-8" X-Rspam-User: X-Rspamd-Server: rspam04 X-Rspamd-Queue-Id: 85FC918001A X-Stat-Signature: sphwxt9oo3ts7tp7mbj6j885etkbr1ko X-HE-Tag: 1677509003-373600 X-HE-Meta: U2FsdGVkX1+27cF/Och38VoF4vkIf7aOh5mi3PKmUVOnYyfRdQkvMZQSdMlBwdiN3rhSRceofN95kBhAkWgYAZm6UEm/5YJAQUYyAfFDw01U3aDaL3wlevnEoJLAEOLWZQABOY8xgzLoim65HvfDMbN3rC1AFQDEUzQ3agNLxEq9aC+0r/ibyyYvhUhUyHF5tB6Gd088EG+lVRBte0e4JZh+NMja1h4xl4tfYnS8uZgPny9mcrV+wEH9hucllGygVWj8gS7zrNbzSRa5zdkzu0ItdaO3IcUt/cXUjI67UzQwFKEi1i0twkGVqur6y4sYuk/tQxlkjaV3VEPfaj5MfUYSLe5BiJEVripsKAZgp9rPC/lXr8vewcgK7hhL0QIPPJc5QrpyyCBFnCfVfzaWsZUXIs3afG9OF0MO6NJk3jDTDMX4sSPPCc77eWmvJgPTRK3xqMe90S789aM0NpVdTaH7/hT/lKbO9ckKFS2k2cSHGHZk6kkzp1hcp4nwpX96f44ubPZQRkmILLPq8WunPzBH7MlwzMSoFcfKB2ZLPX2eukZVJUt4ugcTbRNY8OAalEmQbMwIWZhS0JN9s5NNxEmoMZwh2A7nFoD386a4c2W03aEG5yZ8SmdTZ8MwmBB1bvWgVdrKYF7jZ3zhg9SoCB0y2HXtS+MZYX2+kCyNi8slH1CFQQkMYGwWWN+znnn3yJv/V0S/CdeGGcMepLo/LGOhWUS0FPU6eY5hJr34HgcnSWig+Vc00x0ZPMLsbOI0oWHrTyf0o0WlLFdtuJAxDKjIA+4zAL8elAUYwFSgSQdLr6eZb4cqj5dExL/TCkhw2vz0/lQpNMegtyyRT8P0VfE9g350gzjf5aBYNRuH1JbBMPH+h/j//N2P9dSyh3M7lPYqQWCX2dDuvumeh8MOcS1+MuR0jQwDyKEMpWdzwj7yJ+zj+348xmMubVSVeOLWEdv+twJNNpItpBJ2qyq xkaQ2RPV xK2kllZBUB80eecZGKkJMcLmnWXF4RR6JSibwjm1j0WCB6XZuwbeSHr2PfH2bz26+GspxONiCLR7/k4lcFsrosJ3LwxoJAEckBY1CxaTdg3yE+SKSEW7U5iExIwYKnZxu1g6umXVJfEUbMBiOByC8/bnUWu4L3W2CaAOJhVpoC7gBkD2omaMvkasPu+d86x46MofC5Iqnr4oN5FErKB2BY8Q/WYz+yfUgvdFd/v7CiHYwtU8H3wuAvZliD1viI1MmzJiQ1FoQXT5hSI5xynm4sETsi4SqZNGSPmraVDY2fMIARyBXVTxMKHdLgUWsG5aD6kBcfaWLziglYTGDaqPsSq9bTGzr2AybZmXxxVZpnhF3fWsoZ+xBRjVaoQre2psjPmAjPVozs8j/PJl368pml3m+uqwIRqXgkv6zUvQs4fXj0T7xkxkmOPGZig1sCoGj2urN6ZMBFI35chL02SatYO4Pc+CcN6+6QtknkYczDM4Jqba/OBW9sXs3YTWJR65VjKJiQWk3e0b2wtDM2uFSDpCl0J+h0Yrmdv7ZU38OQx0Hhww4sKEcskCdErLZ/4/qIeqx6EG2TtVKxPBwvzigtTvQos8S8jJXMUfSi+NuHUozU9drAGUMiL2ax61hDLaqTp4TgQc9VtD7Lj4= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Hi David, On Mon, Feb 27, 2023 at 2:31 PM David Hildenbrand wrote: > On 26.02.23 21:13, Geert Uytterhoeven wrote: > > On Fri, Jan 13, 2023 at 6:16 PM David Hildenbrand wrote: > >> Let's support __HAVE_ARCH_PTE_SWP_EXCLUSIVE by stealing one bit > >> from the type. Generic MM currently only uses 5 bits for the type > >> (MAX_SWAPFILES_SHIFT), so the stolen bit is effectively unused. > >> > >> The shift by 2 when converting between PTE and arch-specific swap entry > >> makes the swap PTE layout a little bit harder to decipher. > >> > >> While at it, drop the comment from paulus---copy-and-paste leftover > >> from powerpc where we actually have _PAGE_HASHPTE---and mask the type in > >> __swp_entry_to_pte() as well. > >> > >> Cc: Michal Simek > >> Signed-off-by: David Hildenbrand > > > > Thanks for your patch, which is now commit b5c88f21531c3457 > > ("microblaze/mm: support __HAVE_ARCH_PTE_SWP_EXCLUSIVE") in > > > > Right, it went upstream, so we can only fixup. > > >> arch/m68k/include/asm/mcf_pgtable.h | 4 +-- > > > > What is this m68k change doing here? > > Sorry for not noticing this earlier. > > Thanks for the late review, still valuable :) > > That hunk should have gone into the previous patch, looks like I messed > that up when reworking. > > > > > Furthermore, several things below look strange to me... > > > >> arch/microblaze/include/asm/pgtable.h | 45 +++++++++++++++++++++------ > >> 2 files changed, 37 insertions(+), 12 deletions(-) > >> > >> diff --git a/arch/m68k/include/asm/mcf_pgtable.h b/arch/m68k/include/asm/mcf_pgtable.h > >> index 3f8f4d0e66dd..e573d7b649f7 100644 > >> --- a/arch/m68k/include/asm/mcf_pgtable.h > >> +++ b/arch/m68k/include/asm/mcf_pgtable.h > >> @@ -46,8 +46,8 @@ > >> #define _CACHEMASK040 (~0x060) > >> #define _PAGE_GLOBAL040 0x400 /* 68040 global bit, used for kva descs */ > >> > >> -/* We borrow bit 7 to store the exclusive marker in swap PTEs. */ > >> -#define _PAGE_SWP_EXCLUSIVE 0x080 > >> +/* We borrow bit 24 to store the exclusive marker in swap PTEs. */ > >> +#define _PAGE_SWP_EXCLUSIVE CF_PAGE_NOCACHE > > > > CF_PAGE_NOCACHE is 0x80, so this is still bit 7, thus the new comment > > is wrong? > > You're right, it's still bit 7 (and we use LSB-0 bit numbering in that > file). I'll send a fixup. OK. > >> /* > >> * Externally used page protection values. > >> diff --git a/arch/microblaze/include/asm/pgtable.h b/arch/microblaze/include/asm/pgtable.h > >> index 42f5988e998b..7e3de54bf426 100644 > >> --- a/arch/microblaze/include/asm/pgtable.h > >> +++ b/arch/microblaze/include/asm/pgtable.h > >> @@ -131,10 +131,10 @@ extern pte_t *va_to_pte(unsigned long address); > >> * of the 16 available. Bit 24-26 of the TLB are cleared in the TLB > >> * miss handler. Bit 27 is PAGE_USER, thus selecting the correct > >> * zone. > >> - * - PRESENT *must* be in the bottom two bits because swap cache > >> - * entries use the top 30 bits. Because 4xx doesn't support SMP > >> - * anyway, M is irrelevant so we borrow it for PAGE_PRESENT. Bit 30 > >> - * is cleared in the TLB miss handler before the TLB entry is loaded. > >> + * - PRESENT *must* be in the bottom two bits because swap PTEs use the top > >> + * 30 bits. Because 4xx doesn't support SMP anyway, M is irrelevant so we > >> + * borrow it for PAGE_PRESENT. Bit 30 is cleared in the TLB miss handler > >> + * before the TLB entry is loaded. > > > > So the PowerPC 4xx comment is still here? > > I only dropped the comment above __swp_type(). I guess you mean that we > could also drop the "Because 4xx doesn't support SMP anyway, M is > irrelevant so we borrow it for PAGE_PRESENT." sentence, correct? Not Yes, that's what I meant. > sure about the "Bit 30 is cleared in the TLB miss handler" comment, if > that can similarly be dropped. No idea, didn't check. But if it was copied from PPC, chances are high it's no longer true.... > >> * - All other bits of the PTE are loaded into TLBLO without > >> * * modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for > >> * software PTE bits. We actually use bits 21, 24, 25, and > >> @@ -155,6 +155,9 @@ extern pte_t *va_to_pte(unsigned long address); > >> #define _PAGE_ACCESSED 0x400 /* software: R: page referenced */ > >> #define _PMD_PRESENT PAGE_MASK > >> > >> +/* We borrow bit 24 to store the exclusive marker in swap PTEs. */ > >> +#define _PAGE_SWP_EXCLUSIVE _PAGE_DIRTY > > > > _PAGE_DIRTY is 0x80, so this is also bit 7, thus the new comment is > > wrong? > > In the example, I use MSB-0 bit numbering (which I determined to be > correct in microblaze context eventually, but I got confused a couple a > times because it's very inconsistent). That should be MSB-0 bit 24. Thanks, TIL microblaze uses IBM bit numbering... Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds