From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.4 required=3.0 tests=DKIMWL_WL_MED,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32FD0C43603 for ; Thu, 19 Dec 2019 20:32:48 +0000 (UTC) Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.kernel.org (Postfix) with ESMTP id D78A321D7D for ; Thu, 19 Dec 2019 20:32:47 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="VS7uNRIZ" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D78A321D7D Authentication-Results: mail.kernel.org; dmarc=fail (p=reject dis=none) header.from=google.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=owner-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix) id 6B4F18E017D; Thu, 19 Dec 2019 15:32:47 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id 6665B8E00F5; Thu, 19 Dec 2019 15:32:47 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 5568A8E017D; Thu, 19 Dec 2019 15:32:47 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from forelay.hostedemail.com (smtprelay0179.hostedemail.com [216.40.44.179]) by kanga.kvack.org (Postfix) with ESMTP id 3F45B8E00F5 for ; Thu, 19 Dec 2019 15:32:47 -0500 (EST) Received: from smtpin24.hostedemail.com (10.5.19.251.rfc1918.com [10.5.19.251]) by forelay01.hostedemail.com (Postfix) with SMTP id 10C18180AD81F for ; Thu, 19 Dec 2019 20:32:47 +0000 (UTC) X-FDA: 76283039574.24.salt84_5268105d82c5f X-HE-Tag: salt84_5268105d82c5f X-Filterd-Recvd-Size: 13595 Received: from mail-wr1-f68.google.com (mail-wr1-f68.google.com [209.85.221.68]) by imf24.hostedemail.com (Postfix) with ESMTP for ; Thu, 19 Dec 2019 20:32:46 +0000 (UTC) Received: by mail-wr1-f68.google.com with SMTP id b6so7349348wrq.0 for ; Thu, 19 Dec 2019 12:32:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=ARb5mDSQveEIfXvs9vVwdJYuSobp7c8+9dPylHX7vY8=; b=VS7uNRIZZ8MLEOreXFGfNUO2CHd1si9RvqWaCYvzOM3+aojexZmOiyUhh9rhJeVIax 5j9ugKW6vKVMc2o8Y2ZG9Up08CWE+VVptpfy8u5fQZCI89CWarhM+WBaRkJ874MQK7+y 0uJKlq2uKGBNEL+6cYBo4uUkOq1RoUnGDuN5jpaMiaha7mNnt4YYXCHItlTSddHnrIid 6WiA2rGnhFg1K/ZBAIn/aR2MT6nF/92S82f6dJ6HqAhD3ZOZTRn8HH5ZFKpZW5HTgaSx sy8Lt3wtUgeyKoCcFD+rBTmQzNR1h3KE1GKhqW0JQxQTtrDNwB1NLCOOUKpXUTebO6Ag 9Oww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=ARb5mDSQveEIfXvs9vVwdJYuSobp7c8+9dPylHX7vY8=; b=OdHyVuKyxA5jfFoIPcTC3LT7g+1ZlGRcTyp86qX23m7D6+kqSj9KqNrN7IwMqtUaQJ 1xVoBzagphTQsBac4FRqiTgwd0e1sZa08e3PDU0XvgkgINnXYMKETjrUD50X2SP8gz0i rdI2t+MBVyQ5amcCTpAy9stNiJ0293l4vMDbKzr1714W87vpItJErzCAl8EBSbpJrjAY WclvZ+GpcQ0Q6HUNuLqLsm/j+s5mvrV4yTjIqr0SYDtUdBVeOHOt/yeItAs/kNGIWSbB INWAt4NazMF6QbdWiQFWQRIr4r5eaECK1EvuoO2UXybGz0w5j5Fm7wVRNJrFIfuD+nCL mQTQ== X-Gm-Message-State: APjAAAVwnjQR5f9KgQzsOsBCBHnDMAoNF8tY/AQpZS9HdElfH2x8RG6M HT0MEuvW8cLxPtH8L7HG2kUe1Nrq8vnDvqRugHssxg== X-Google-Smtp-Source: APXvYqyVQDM1TNKi2CDKuckeKwTsTs7+kz0LrmiO++KrHbrxaBx0jZpjzln/geYaoSRD8UwsRcYuADmjIj+d2QEQve8= X-Received: by 2002:a5d:4984:: with SMTP id r4mr10905135wrq.137.1576787563681; Thu, 19 Dec 2019 12:32:43 -0800 (PST) MIME-Version: 1.0 References: <20191211184027.20130-1-catalin.marinas@arm.com> <20191211184027.20130-20-catalin.marinas@arm.com> In-Reply-To: <20191211184027.20130-20-catalin.marinas@arm.com> From: Peter Collingbourne Date: Thu, 19 Dec 2019 12:32:31 -0800 Message-ID: Subject: Re: [PATCH 19/22] arm64: mte: Allow user control of the tag check mode via prctl() To: Catalin Marinas , Evgenii Stepanov , Kostya Serebryany Cc: Linux ARM , linux-arch@vger.kernel.org, Richard Earnshaw , Szabolcs Nagy , Marc Zyngier , Kevin Brodsky , linux-mm@kvack.org, Andrey Konovalov , Vincenzo Frascino , Will Deacon Content-Type: text/plain; charset="UTF-8" X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On Wed, Dec 11, 2019 at 10:45 AM Catalin Marinas wrote: > > By default, even if PROT_MTE is set on a memory range, there is no tag > check fault reporting (SIGSEGV). Introduce a set of option to the > exiting prctl(PR_SET_TAGGED_ADDR_CTRL) to allow user control of the tag > check fault mode: > > PR_MTE_TCF_NONE - no reporting (default) > PR_MTE_TCF_SYNC - synchronous tag check fault reporting > PR_MTE_TCF_ASYNC - asynchronous tag check fault reporting > > These options translate into the corresponding SCTLR_EL1.TCF0 bitfield, > context-switched by the kernel. Note that uaccess done by the kernel is > not checked and cannot be configured by the user. > > Signed-off-by: Catalin Marinas > --- > arch/arm64/include/asm/processor.h | 3 + > arch/arm64/kernel/process.c | 119 +++++++++++++++++++++++++++-- > include/uapi/linux/prctl.h | 6 ++ > 3 files changed, 123 insertions(+), 5 deletions(-) > > diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h > index 5ba63204d078..91aa270afc7d 100644 > --- a/arch/arm64/include/asm/processor.h > +++ b/arch/arm64/include/asm/processor.h > @@ -148,6 +148,9 @@ struct thread_struct { > #ifdef CONFIG_ARM64_PTR_AUTH > struct ptrauth_keys keys_user; > #endif > +#ifdef CONFIG_ARM64_MTE > + u64 sctlr_tcf0; > +#endif > }; > > static inline void arch_thread_struct_whitelist(unsigned long *offset, > diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c > index dd98d539894e..47ce98f47253 100644 > --- a/arch/arm64/kernel/process.c > +++ b/arch/arm64/kernel/process.c > @@ -317,11 +317,22 @@ static void flush_tagged_addr_state(void) > clear_thread_flag(TIF_TAGGED_ADDR); > } > > +#ifdef CONFIG_ARM64_MTE > +static void flush_mte_state(void) > +{ > + if (!system_supports_mte()) > + return; > + > + /* clear any pending asynchronous tag fault */ > + clear_thread_flag(TIF_MTE_ASYNC_FAULT); > + /* disable tag checking */ > + current->thread.sctlr_tcf0 = 0; > +} > +#else > static void flush_mte_state(void) > { > - if (system_supports_mte()) > - clear_thread_flag(TIF_MTE_ASYNC_FAULT); > } > +#endif > > void flush_thread(void) > { > @@ -484,6 +495,29 @@ static void ssbs_thread_switch(struct task_struct *next) > set_ssbs_bit(regs); > } > > +#ifdef CONFIG_ARM64_MTE > +static void update_sctlr_el1_tcf0(u64 tcf0) > +{ > + /* no need for ISB since this only affects EL0, implicit with ERET */ > + sysreg_clear_set(sctlr_el1, SCTLR_EL1_TCF0_MASK, tcf0); > +} > + > +/* Handle MTE thread switch */ > +static void mte_thread_switch(struct task_struct *next) > +{ > + if (!system_supports_mte()) > + return; > + > + /* avoid expensive SCTLR_EL1 accesses if no change */ > + if (current->thread.sctlr_tcf0 != next->thread.sctlr_tcf0) > + update_sctlr_el1_tcf0(next->thread.sctlr_tcf0); I don't entirely understand why yet, but I've found that this check is insufficient for ensuring consistency between SCTLR_EL1.TCF0 and sctlr_tcf0. In my Android test environment with some processes having sctlr_tcf0=SCTLR_EL1_TCF0_SYNC and others having sctlr_tcf0=0, I am seeing intermittent tag failures coming from the sctlr_tcf0=0 processes. With this patch: diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c index ef3bfa2bf2b1..4e5d02520a51 100644 --- a/arch/arm64/mm/fault.c +++ b/arch/arm64/mm/fault.c @@ -663,6 +663,8 @@ static int do_sea(unsigned long addr, unsigned int esr, struct pt_regs *regs) static int do_tag_check_fault(unsigned long addr, unsigned int esr, struct pt_regs *regs) { + printk(KERN_ERR "do_tag_check_fault %lx %lx\n", + current->thread.sctlr_tcf0, read_sysreg(sctlr_el1)); do_bad_area(addr, esr, regs); return 0; } I see dmesg output like this: [ 15.249216] do_tag_check_fault 0 c60fc64791d showing that SCTLR_EL1.TCF0 became inconsistent with sctlr_tcf0. This patch fixes the problem for me: diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c index fba89c9f070b..fb012f0baa12 100644 --- a/arch/arm64/kernel/process.c +++ b/arch/arm64/kernel/process.c @@ -518,9 +518,7 @@ static void mte_thread_switch(struct task_struct *next) if (!system_supports_mte()) return; - /* avoid expensive SCTLR_EL1 accesses if no change */ - if (current->thread.sctlr_tcf0 != next->thread.sctlr_tcf0) - update_sctlr_el1_tcf0(next->thread.sctlr_tcf0); + update_sctlr_el1_tcf0(next->thread.sctlr_tcf0); update_gcr_el1_excl(next->thread.gcr_excl); } #else @@ -643,15 +641,8 @@ static long set_mte_ctrl(unsigned long arg) return -EINVAL; } - /* - * mte_thread_switch() checks current->thread.sctlr_tcf0 as an - * optimisation. Disable preemption so that it does not see - * the variable update before the SCTLR_EL1.TCF0 one. - */ - preempt_disable(); current->thread.sctlr_tcf0 = tcf0; update_sctlr_el1_tcf0(tcf0); - preempt_enable(); current->thread.gcr_excl = (arg & PR_MTE_EXCL_MASK) >> PR_MTE_EXCL_SHIFT; update_gcr_el1_excl(current->thread.gcr_excl); Since sysreg_clear_set only sets the sysreg if it ended up changing, I wouldn't expect this to cause a significant performance hit unless just reading SCTLR_EL1 is expensive. That being said, if the inconsistency is indicative of a deeper problem, we should probably address that. Peter > +} > +#else > +static void mte_thread_switch(struct task_struct *next) > +{ > +} > +#endif > + > /* > * We store our current task in sp_el0, which is clobbered by userspace. Keep a > * shadow copy so that we can restore this upon entry from userspace. > @@ -514,6 +548,7 @@ __notrace_funcgraph struct task_struct *__switch_to(struct task_struct *prev, > uao_thread_switch(next); > ptrauth_thread_switch(next); > ssbs_thread_switch(next); > + mte_thread_switch(next); > > /* > * Complete any pending TLB or cache maintenance on this CPU in case > @@ -574,6 +609,67 @@ void arch_setup_new_exec(void) > ptrauth_thread_init_user(current); > } > > +#ifdef CONFIG_ARM64_MTE > +static long set_mte_ctrl(unsigned long arg) > +{ > + u64 tcf0; > + > + if (!system_supports_mte()) > + return 0; > + > + switch (arg & PR_MTE_TCF_MASK) { > + case PR_MTE_TCF_NONE: > + tcf0 = 0; > + break; > + case PR_MTE_TCF_SYNC: > + tcf0 = SCTLR_EL1_TCF0_SYNC; > + break; > + case PR_MTE_TCF_ASYNC: > + tcf0 = SCTLR_EL1_TCF0_ASYNC; > + break; > + default: > + return -EINVAL; > + } > + > + /* > + * mte_thread_switch() checks current->thread.sctlr_tcf0 as an > + * optimisation. Disable preemption so that it does not see > + * the variable update before the SCTLR_EL1.TCF0 one. > + */ > + preempt_disable(); > + current->thread.sctlr_tcf0 = tcf0; > + update_sctlr_el1_tcf0(tcf0); > + preempt_enable(); > + > + return 0; > +} > + > +static long get_mte_ctrl(void) > +{ > + if (!system_supports_mte()) > + return 0; > + > + switch (current->thread.sctlr_tcf0) { > + case SCTLR_EL1_TCF0_SYNC: > + return PR_MTE_TCF_SYNC; > + case SCTLR_EL1_TCF0_ASYNC: > + return PR_MTE_TCF_ASYNC; > + } > + > + return 0; > +} > +#else > +static long set_mte_ctrl(unsigned long arg) > +{ > + return 0; > +} > + > +static long get_mte_ctrl(void) > +{ > + return 0; > +} > +#endif > + > #ifdef CONFIG_ARM64_TAGGED_ADDR_ABI > /* > * Control the relaxed ABI allowing tagged user addresses into the kernel. > @@ -582,9 +678,15 @@ static unsigned int tagged_addr_disabled; > > long set_tagged_addr_ctrl(unsigned long arg) > { > + unsigned long valid_mask = PR_TAGGED_ADDR_ENABLE; > + > if (is_compat_task()) > return -EINVAL; > - if (arg & ~PR_TAGGED_ADDR_ENABLE) > + > + if (system_supports_mte()) > + valid_mask |= PR_MTE_TCF_MASK; > + > + if (arg & ~valid_mask) > return -EINVAL; > > /* > @@ -594,6 +696,9 @@ long set_tagged_addr_ctrl(unsigned long arg) > if (arg & PR_TAGGED_ADDR_ENABLE && tagged_addr_disabled) > return -EINVAL; > > + if (set_mte_ctrl(arg) != 0) > + return -EINVAL; > + > update_thread_flag(TIF_TAGGED_ADDR, arg & PR_TAGGED_ADDR_ENABLE); > > return 0; > @@ -601,13 +706,17 @@ long set_tagged_addr_ctrl(unsigned long arg) > > long get_tagged_addr_ctrl(void) > { > + long ret = 0; > + > if (is_compat_task()) > return -EINVAL; > > if (test_thread_flag(TIF_TAGGED_ADDR)) > - return PR_TAGGED_ADDR_ENABLE; > + ret = PR_TAGGED_ADDR_ENABLE; > > - return 0; > + ret |= get_mte_ctrl(); > + > + return ret; > } > > /* > diff --git a/include/uapi/linux/prctl.h b/include/uapi/linux/prctl.h > index 7da1b37b27aa..5e9323e66a38 100644 > --- a/include/uapi/linux/prctl.h > +++ b/include/uapi/linux/prctl.h > @@ -233,5 +233,11 @@ struct prctl_mm_map { > #define PR_SET_TAGGED_ADDR_CTRL 55 > #define PR_GET_TAGGED_ADDR_CTRL 56 > # define PR_TAGGED_ADDR_ENABLE (1UL << 0) > +/* MTE tag check fault modes */ > +# define PR_MTE_TCF_SHIFT 1 > +# define PR_MTE_TCF_NONE (0UL << PR_MTE_TCF_SHIFT) > +# define PR_MTE_TCF_SYNC (1UL << PR_MTE_TCF_SHIFT) > +# define PR_MTE_TCF_ASYNC (2UL << PR_MTE_TCF_SHIFT) > +# define PR_MTE_TCF_MASK (3UL << PR_MTE_TCF_SHIFT) > > #endif /* _LINUX_PRCTL_H */ > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel