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From: Andy Lutomirski <luto@kernel.org>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: Andy Lutomirski <luto@kernel.org>, X86 ML <x86@kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	Borislav Petkov <bp@alien8.de>,
	Linus Torvalds <torvalds@linux-foundation.org>,
	Andrew Morton <akpm@linux-foundation.org>,
	Mel Gorman <mgorman@suse.de>,
	"linux-mm@kvack.org" <linux-mm@kvack.org>,
	Nadav Amit <nadav.amit@gmail.com>, Rik van Riel <riel@redhat.com>,
	Dave Hansen <dave.hansen@intel.com>,
	Arjan van de Ven <arjan@linux.intel.com>,
	Peter Zijlstra <peterz@infradead.org>,
	Andrew Banman <abanman@sgi.com>, Mike Travis <travis@sgi.com>,
	Dimitri Sivanich <sivanich@sgi.com>,
	Juergen Gross <jgross@suse.com>,
	Boris Ostrovsky <boris.ostrovsky@oracle.com>
Subject: Re: [PATCH v3 06/11] x86/mm: Rework lazy TLB mode and TLB freshness tracking
Date: Wed, 21 Jun 2017 09:04:48 -0700	[thread overview]
Message-ID: <CALCETrXkRQDWQH6oZfg4-36i4sgxjhfXmfaatHmmgXKVwtX+qA@mail.gmail.com> (raw)
In-Reply-To: <alpine.DEB.2.20.1706211033340.2328@nanos>

On Wed, Jun 21, 2017 at 2:01 AM, Thomas Gleixner <tglx@linutronix.de> wrote:
> On Tue, 20 Jun 2017, Andy Lutomirski wrote:
>> -/*
>> - * The flush IPI assumes that a thread switch happens in this order:
>> - * [cpu0: the cpu that switches]
>> - * 1) switch_mm() either 1a) or 1b)
>> - * 1a) thread switch to a different mm
>> - * 1a1) set cpu_tlbstate to TLBSTATE_OK
>> - *   Now the tlb flush NMI handler flush_tlb_func won't call leave_mm
>> - *   if cpu0 was in lazy tlb mode.
>> - * 1a2) update cpu active_mm
>> - *   Now cpu0 accepts tlb flushes for the new mm.
>> - * 1a3) cpu_set(cpu, new_mm->cpu_vm_mask);
>> - *   Now the other cpus will send tlb flush ipis.
>> - * 1a4) change cr3.
>> - * 1a5) cpu_clear(cpu, old_mm->cpu_vm_mask);
>> - *   Stop ipi delivery for the old mm. This is not synchronized with
>> - *   the other cpus, but flush_tlb_func ignore flush ipis for the wrong
>> - *   mm, and in the worst case we perform a superfluous tlb flush.
>> - * 1b) thread switch without mm change
>> - *   cpu active_mm is correct, cpu0 already handles flush ipis.
>> - * 1b1) set cpu_tlbstate to TLBSTATE_OK
>> - * 1b2) test_and_set the cpu bit in cpu_vm_mask.
>> - *   Atomically set the bit [other cpus will start sending flush ipis],
>> - *   and test the bit.
>> - * 1b3) if the bit was 0: leave_mm was called, flush the tlb.
>> - * 2) switch %%esp, ie current
>> - *
>> - * The interrupt must handle 2 special cases:
>> - * - cr3 is changed before %%esp, ie. it cannot use current->{active_,}mm.
>> - * - the cpu performs speculative tlb reads, i.e. even if the cpu only
>> - *   runs in kernel space, the cpu could load tlb entries for user space
>> - *   pages.
>> - *
>> - * The good news is that cpu_tlbstate is local to each cpu, no
>> - * write/read ordering problems.
>
> While the new code is really well commented, it would be a good thing to
> have a single place where all of this including the ordering constraints
> are documented.

I'll look at the end of the whole series and see if I can come up with
something good.

>
>> @@ -215,12 +200,13 @@ static void flush_tlb_func_common(const struct flush_tlb_info *f,
>>       VM_WARN_ON(this_cpu_read(cpu_tlbstate.ctxs[0].ctx_id) !=
>>                  loaded_mm->context.ctx_id);
>>
>> -     if (this_cpu_read(cpu_tlbstate.state) != TLBSTATE_OK) {
>> +     if (!cpumask_test_cpu(smp_processor_id(), mm_cpumask(loaded_mm))) {
>>               /*
>> -              * leave_mm() is adequate to handle any type of flush, and
>> -              * we would prefer not to receive further IPIs.
>> +              * We're in lazy mode -- don't flush.  We can get here on
>> +              * remote flushes due to races and on local flushes if a
>> +              * kernel thread coincidentally flushes the mm it's lazily
>> +              * still using.
>
> Ok. That's more informative.
>
> Reviewed-by: Thomas Gleixner <tglx@linutronix.de>

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  reply	other threads:[~2017-06-21 16:05 UTC|newest]

Thread overview: 76+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-06-21  5:22 [PATCH v3 00/11] PCID and improved laziness Andy Lutomirski
2017-06-21  5:22 ` [PATCH v3 01/11] x86/mm: Don't reenter flush_tlb_func_common() Andy Lutomirski
2017-06-21  8:01   ` Thomas Gleixner
2017-06-21  8:49   ` Borislav Petkov
2017-06-21 15:15     ` Andy Lutomirski
2017-06-21 23:26   ` Nadav Amit
2017-06-22  2:27     ` Andy Lutomirski
2017-06-22  7:32       ` Ingo Molnar
2017-06-21  5:22 ` [PATCH v3 02/11] x86/ldt: Simplify LDT switching logic Andy Lutomirski
2017-06-21  8:03   ` Thomas Gleixner
2017-06-21  9:40   ` Borislav Petkov
2017-06-21  5:22 ` [PATCH v3 03/11] x86/mm: Remove reset_lazy_tlbstate() Andy Lutomirski
2017-06-21  8:03   ` Thomas Gleixner
2017-06-21  9:50   ` Borislav Petkov
2017-06-21  5:22 ` [PATCH v3 04/11] x86/mm: Give each mm TLB flush generation a unique ID Andy Lutomirski
2017-06-21  8:05   ` Thomas Gleixner
2017-06-21 10:33   ` Borislav Petkov
2017-06-21 15:23     ` Andy Lutomirski
2017-06-21 17:06       ` Borislav Petkov
2017-06-21 17:43   ` Borislav Petkov
2017-06-22  2:34     ` Andy Lutomirski
2017-06-21  5:22 ` [PATCH v3 05/11] x86/mm: Track the TLB's tlb_gen and update the flushing algorithm Andy Lutomirski
2017-06-21  8:32   ` Thomas Gleixner
2017-06-21 15:11     ` Andy Lutomirski
2017-06-21 18:44   ` Borislav Petkov
2017-06-22  2:46     ` Andy Lutomirski
2017-06-22  7:24       ` Borislav Petkov
2017-06-22 14:48         ` Andy Lutomirski
2017-06-22 14:59           ` Borislav Petkov
2017-06-22 15:55             ` Andy Lutomirski
2017-06-22 17:22               ` Borislav Petkov
2017-06-22 18:08                 ` Andy Lutomirski
2017-06-23  8:42                   ` Borislav Petkov
2017-06-23 15:46                     ` Andy Lutomirski
2017-06-21  5:22 ` [PATCH v3 06/11] x86/mm: Rework lazy TLB mode and TLB freshness tracking Andy Lutomirski
2017-06-21  9:01   ` Thomas Gleixner
2017-06-21 16:04     ` Andy Lutomirski [this message]
2017-06-21 17:29       ` Borislav Petkov
2017-06-22 14:50   ` Borislav Petkov
2017-06-22 17:47     ` Andy Lutomirski
2017-06-22 19:05       ` Borislav Petkov
2017-07-27 19:53       ` Andrew Banman
2017-07-28  2:05         ` Andy Lutomirski
2017-06-23 13:34   ` Boris Ostrovsky
2017-06-23 15:22     ` Andy Lutomirski
2017-06-21  5:22 ` [PATCH v3 07/11] x86/mm: Stop calling leave_mm() in idle code Andy Lutomirski
2017-06-21  9:22   ` Thomas Gleixner
2017-06-21 15:16     ` Andy Lutomirski
2017-06-23  9:07   ` Borislav Petkov
2017-06-21  5:22 ` [PATCH v3 08/11] x86/mm: Disable PCID on 32-bit kernels Andy Lutomirski
2017-06-21  9:26   ` Thomas Gleixner
2017-06-23  9:24   ` Borislav Petkov
2017-06-21  5:22 ` [PATCH v3 09/11] x86/mm: Add nopcid to turn off PCID Andy Lutomirski
2017-06-21  9:27   ` Thomas Gleixner
2017-06-23  9:34   ` Borislav Petkov
2017-06-21  5:22 ` [PATCH v3 10/11] x86/mm: Enable CR4.PCIDE on supported systems Andy Lutomirski
2017-06-21  9:39   ` Thomas Gleixner
2017-06-21 13:40     ` Thomas Gleixner
2017-06-21 20:34     ` Andy Lutomirski
2017-06-23 11:50   ` Borislav Petkov
2017-06-23 15:28     ` Andy Lutomirski
2017-06-23 13:35   ` Boris Ostrovsky
2017-06-21  5:22 ` [PATCH v3 11/11] x86/mm: Try to preserve old TLB entries using PCID Andy Lutomirski
2017-06-21 13:38   ` Thomas Gleixner
2017-06-21 13:40     ` Thomas Gleixner
2017-06-22  2:57     ` Andy Lutomirski
2017-06-22 12:21       ` Thomas Gleixner
2017-06-22 18:12         ` Andy Lutomirski
2017-06-22 21:22           ` Thomas Gleixner
2017-06-23  3:09             ` Andy Lutomirski
2017-06-23  7:29               ` Thomas Gleixner
2017-06-22 16:09   ` Nadav Amit
2017-06-22 18:10     ` Andy Lutomirski
2017-06-26 15:58   ` Borislav Petkov
2017-06-21 18:23 ` [PATCH v3 00/11] PCID and improved laziness Linus Torvalds
2017-06-22  5:19   ` Andy Lutomirski

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