From: Andy Lutomirski <luto@kernel.org>
To: "Levin, Alexander (Sasha Levin)" <alexander.levin@verizon.com>
Cc: Andy Lutomirski <luto@kernel.org>,
"x86@kernel.org" <x86@kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Borislav Petkov <bp@alien8.de>,
Linus Torvalds <torvalds@linux-foundation.org>,
Andrew Morton <akpm@linux-foundation.org>,
Mel Gorman <mgorman@suse.de>,
"linux-mm@kvack.org" <linux-mm@kvack.org>,
Nadav Amit <nadav.amit@gmail.com>, Rik van Riel <riel@redhat.com>,
Dave Hansen <dave.hansen@intel.com>,
Arjan van de Ven <arjan@linux.intel.com>,
Peter Zijlstra <peterz@infradead.org>
Subject: Re: [PATCH v2 00/10] PCID and improved laziness
Date: Sun, 18 Jun 2017 21:43:54 -0700 [thread overview]
Message-ID: <CALCETrVp9h5=PB6mu5_KZPKkj1YqpuYva=ncPxT0tfAgtA9Hdw@mail.gmail.com> (raw)
In-Reply-To: <20170618212948.mt33zbajt5n6saed@sasha-lappy>
On Sun, Jun 18, 2017 at 2:29 PM, Levin, Alexander (Sasha Levin)
<alexander.levin@verizon.com> wrote:
> On Tue, Jun 13, 2017 at 09:56:18PM -0700, Andy Lutomirski wrote:
>>There are three performance benefits here:
>>
>>1. TLB flushing is slow. (I.e. the flush itself takes a while.)
>> This avoids many of them when switching tasks by using PCID. In
>> a stupid little benchmark I did, it saves about 100ns on my laptop
>> per context switch. I'll try to improve that benchmark.
>>
>>2. Mms that have been used recently on a given CPU might get to keep
>> their TLB entries alive across process switches with this patch
>> set. TLB fills are pretty fast on modern CPUs, but they're even
>> faster when they don't happen.
>>
>>3. Lazy TLB is way better. We used to do two stupid things when we
>> ran kernel threads: we'd send IPIs to flush user contexts on their
>> CPUs and then we'd write to CR3 for no particular reason as an excuse
>> to stop further IPIs. With this patch, we do neither.
>>
>>This will, in general, perform suboptimally if paravirt TLB flushing
>>is in use (currently just Xen, I think, but Hyper-V is in the works).
>>The code is structured so we could fix it in one of two ways: we
>>could take a spinlock when touching the percpu state so we can update
>>it remotely after a paravirt flush, or we could be more careful about
>>our exactly how we access the state and use cmpxchg16b to do atomic
>>remote updates. (On SMP systems without cmpxchg16b, we'd just skip
>>the optimization entirely.)
>
> Hey Andy,
>
> I've started seeing the following in -next:
>
> ------------[ cut here ]------------
> kernel BUG at arch/x86/mm/tlb.c:47!
...
> Call Trace:
> flush_tlb_func_local arch/x86/mm/tlb.c:239 [inline]
> flush_tlb_mm_range+0x26d/0x370 arch/x86/mm/tlb.c:317
> flush_tlb_page arch/x86/include/asm/tlbflush.h:253 [inline]
I think I see what's going on, and it should be fixed in the PCID
series. I'll split out the fix.
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prev parent reply other threads:[~2017-06-19 4:44 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-14 4:56 Andy Lutomirski
2017-06-14 4:56 ` [PATCH v2 01/10] x86/ldt: Simplify LDT switching logic Andy Lutomirski
2017-06-15 18:53 ` Rik van Riel
2017-06-14 4:56 ` [PATCH v2 02/10] x86/mm: Remove reset_lazy_tlbstate() Andy Lutomirski
2017-06-15 19:29 ` Rik van Riel
2017-06-14 4:56 ` [PATCH v2 03/10] x86/mm: Give each mm TLB flush generation a unique ID Andy Lutomirski
2017-06-14 15:54 ` Dave Hansen
2017-06-14 17:16 ` Andy Lutomirski
2017-06-14 4:56 ` [PATCH v2 04/10] x86/mm: Track the TLB's tlb_gen and update the flushing algorithm Andy Lutomirski
2017-06-14 4:56 ` [PATCH v2 05/10] x86/mm: Rework lazy TLB mode and TLB freshness tracking Andy Lutomirski
2017-06-14 6:09 ` Juergen Gross
2017-06-19 22:00 ` Andy Lutomirski
2017-06-14 22:33 ` Dave Hansen
2017-06-14 22:42 ` Andy Lutomirski
2017-06-18 8:06 ` Nadav Amit
2017-06-19 21:58 ` Andy Lutomirski
2017-06-14 4:56 ` [PATCH v2 06/10] x86/mm: Stop calling leave_mm() in idle code Andy Lutomirski
2017-06-14 4:56 ` [PATCH v2 07/10] x86/mm: Disable PCID on 32-bit kernels Andy Lutomirski
2017-06-14 4:56 ` [PATCH v2 08/10] x86/mm: Add nopcid to turn off PCID Andy Lutomirski
2017-06-14 4:56 ` [PATCH v2 09/10] x86/mm: Enable CR4.PCIDE on supported systems Andy Lutomirski
2017-06-14 5:30 ` Juergen Gross
2017-06-14 4:56 ` [PATCH v2 10/10] x86/mm: Try to preserve old TLB entries using PCID Andy Lutomirski
2017-06-18 6:26 ` Nadav Amit
2017-06-19 22:02 ` Andy Lutomirski
2017-06-19 22:53 ` Nadav Amit
2017-06-19 23:04 ` Nadav Amit
2017-06-14 22:18 ` [PATCH v2 00/10] PCID and improved laziness Dave Hansen
2017-06-14 22:48 ` Andy Lutomirski
[not found] ` <CA+55aFw_PYteXjaFZw0vkn4XgOomaqN3JWN-NDh_HdaN8Jb0ZA@mail.gmail.com>
[not found] ` <CA+55aFxzXmg3Kkk+NaXYFy4JsQpbUcZ+CGTgTqAdOsOGqA_E_Q@mail.gmail.com>
2017-06-14 22:58 ` Linus Torvalds
2017-06-18 21:29 ` Levin, Alexander (Sasha Levin)
2017-06-19 4:43 ` Andy Lutomirski [this message]
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