From: Balbir Singh <bsingharora@gmail.com>
To: Jerome Glisse <jglisse@redhat.com>
Cc: lsf-pc <lsf-pc@lists.linux-foundation.org>,
linux-mm <linux-mm@kvack.org>,
Anshuman Khandual <khandual@linux.vnet.ibm.com>,
Dan Williams <dan.j.williams@intel.com>,
John Hubbard <jhubbard@nvidia.com>,
Jonathan Masters <jcm@redhat.com>,
Ross Zwisler <ross.zwisler@linux.intel.com>
Subject: Re: [LSF/MM TOPIC] CAPI/CCIX cache coherent device memory (NUMA too ?)
Date: Wed, 17 Jan 2018 21:59:40 +0530 [thread overview]
Message-ID: <CAKTCnznQ95Ao5hOEH=pecaoU9G9xYvitV64shf8S39vzfH+uyA@mail.gmail.com> (raw)
In-Reply-To: <20180116210321.GB8801@redhat.com>
On Wed, Jan 17, 2018 at 2:33 AM, Jerome Glisse <jglisse@redhat.com> wrote:
> CAPI (on IBM Power8 and 9) and CCIX are two new standard that
> build on top of existing interconnect (like PCIE) and add the
> possibility for cache coherent access both way (from CPU to
> device memory and from device to main memory). This extend
> what we are use to with PCIE (where only device to main memory
> can be cache coherent but not CPU to device memory).
>
> How is this memory gonna be expose to the kernel and how the
> kernel gonna expose this to user space is the topic i want to
> discuss. I believe this is highly device specific for instance
> for GPU you want the device memory allocation and usage to be
> under the control of the GPU device driver. Maybe other type
> of device want different strategy.
>
> The HMAT patchset is partialy related to all this as it is about
> exposing different type of memory available in a system for CPU
> (HBM, main memory, ...) and some of their properties (bandwidth,
> latency, ...).
>
>
> We can start by looking at how CAPI and CCIX plan to expose this
> to the kernel and try to list some of the type of devices we
> expect to see. Discussion can then happen on how to represent this
> internaly to the kernel and how to expose this to userspace.
>
> Note this might also trigger discussion on a NUMA like model or
> on extending/replacing it by something more generic.
>
Yes, I agree. I've had some experience with both NUMA and HMM/CDM
models. I think we should compare and contrast the trade-offs
and also discuss how we want to expose some of the ZONE_DEVICE
information back to user space.
>
> Peoples (alphabetical order on first name) sorry if i missed
> anyone:
> "Anshuman Khandual" <khandual@linux.vnet.ibm.com>
> "Balbir Singh" <bsingharora@gmail.com>
> "Dan Williams" <dan.j.williams@intel.com>
> "John Hubbard" <jhubbard@nvidia.com>
> "Jonathan Masters" <jcm@redhat.com>
> "Ross Zwisler" <ross.zwisler@linux.intel.com>
I'd love to be there if invited.
Thanks,
Balbir Singh.
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next prev parent reply other threads:[~2018-01-17 16:29 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-16 21:03 Jerome Glisse
2018-01-17 1:32 ` Liubo(OS Lab)
2018-01-17 16:43 ` Balbir Singh
2018-01-17 1:55 ` Figo.zhang
2018-01-17 2:30 ` Jerome Glisse
2018-01-17 16:29 ` Balbir Singh [this message]
2018-01-19 5:14 ` John Hubbard
2018-01-26 18:47 ` Ross Zwisler
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