From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94405C63697 for ; Tue, 10 Nov 2020 11:21:32 +0000 (UTC) Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.kernel.org (Postfix) with ESMTP id E7CB320780 for ; Tue, 10 Nov 2020 11:21:31 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=kernel.org header.i=@kernel.org header.b="Uh+3Fb6C" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E7CB320780 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=owner-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix) id D19AD6B0036; Tue, 10 Nov 2020 06:21:30 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id CC92A6B005C; Tue, 10 Nov 2020 06:21:30 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id B913E6B005D; Tue, 10 Nov 2020 06:21:30 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from forelay.hostedemail.com (smtprelay0196.hostedemail.com [216.40.44.196]) by kanga.kvack.org (Postfix) with ESMTP id 8C2886B0036 for ; Tue, 10 Nov 2020 06:21:30 -0500 (EST) Received: from smtpin07.hostedemail.com (10.5.19.251.rfc1918.com [10.5.19.251]) by forelay01.hostedemail.com (Postfix) with ESMTP id 3028E180AD804 for ; Tue, 10 Nov 2020 11:21:30 +0000 (UTC) X-FDA: 77468267940.07.scene47_010b63b272f4 Received: from filter.hostedemail.com (10.5.16.251.rfc1918.com [10.5.16.251]) by smtpin07.hostedemail.com (Postfix) with ESMTP id 12C3C1803F9A8 for ; Tue, 10 Nov 2020 11:21:30 +0000 (UTC) X-HE-Tag: scene47_010b63b272f4 X-Filterd-Recvd-Size: 5631 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by imf03.hostedemail.com (Postfix) with ESMTP for ; Tue, 10 Nov 2020 11:21:29 +0000 (UTC) Received: from mail-ot1-f47.google.com (mail-ot1-f47.google.com [209.85.210.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 05139216C4 for ; Tue, 10 Nov 2020 11:21:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1605007288; bh=PS/kHAZVQF4vdeKJ/VmmbLCqTWoEVOY/pzMF/p4PlTo=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=Uh+3Fb6C6Atqe1voXPCA2r1FLJs72jKHGSr7B6kbIXsy78QkqElOGKvZv5BdekvWx lzjf9rrEmqnFeLs+N6vmnXA7mJSWOTIEJJgwAcoMWQ5bay60wvJFT355zkxWYuI93e VFOAzv80wFRQCVrq27haai3hE46vNHO62KFcpXE0= Received: by mail-ot1-f47.google.com with SMTP id g19so12094044otp.13 for ; Tue, 10 Nov 2020 03:21:27 -0800 (PST) X-Gm-Message-State: AOAM530TfThftzAJ2fHVe+2CWGfcrBJvy8x/U+07m1o/VVqGxt7CmNXm +Gv3jFUxXmZKOp+BrpPHD0WktTgzfLcKYKeaDUc= X-Google-Smtp-Source: ABdhPJydWZ+qVqjNBQKB7NRqQskTI00kbru8Yb5/ZqvL2ydH3aQAWKPfoTlgG1dw2AtliyGv5WSBYdJxp7kkZUtof5M= X-Received: by 2002:a9d:23a6:: with SMTP id t35mr13003260otb.210.1605007287164; Tue, 10 Nov 2020 03:21:27 -0800 (PST) MIME-Version: 1.0 References: <20201108064659.GD301837@kernel.org> <7782fb694a6b0c500e8f32ecf895b2bf@agner.ch> <20201110095806.GH301837@kernel.org> In-Reply-To: <20201110095806.GH301837@kernel.org> From: Arnd Bergmann Date: Tue, 10 Nov 2020 12:21:11 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH] mm/zsmalloc: include sparsemem.h for MAX_PHYSMEM_BITS To: Mike Rapoport Cc: Stefan Agner , Minchan Kim , ngupta@vflare.org, Sergey Senozhatsky , Andrew Morton , sjenning@linux.vnet.ibm.com, gregkh , Arnd Bergmann , Linux-MM , "linux-kernel@vger.kernel.org" Content-Type: text/plain; charset="UTF-8" X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On Tue, Nov 10, 2020 at 10:58 AM Mike Rapoport wrote: > > > > > > asm/sparsemem.h is not available on some architectures. > > > It's better to use linux/mmzone.h instead. Ah, I missed that, too. > > Hm, linux/mmzone.h only includes asm/sparsemem.h when CONFIG_SPARSEMEM > > is enabled. However, on ARM at least I can have configurations without > > CONFIG_SPARSEMEM and physical address extension on (e.g. > > multi_v7_defconfig + CONFIG_LPAE + CONFIG_ZSMALLOC). > > > > While sparsemem seems to be a good idea with LPAE it really seems not > > required (see also https://lore.kernel.org/patchwork/patch/567589/). > > > > There seem to be also other architectures which define MAX_PHYSMEM_BITS > > only when SPARSEMEM is enabled, e.g. > > arch/riscv/include/asm/sparsemem.h... > > > > Not sure how to get out of this.. Maybe make ZSMALLOC dependent on > > SPARSEMEM? It feels a bit silly restricting ZSMALLOC selection only due > > to a compile time define... > > I think we can define MAX_POSSIBLE_PHYSMEM_BITS in one of > arch/arm/inclide/asm/pgtable-{2,3}level-*.h headers to values supported > by !LPAE and LPAE. Good idea. I wonder what other architectures need the same though. Here are some I found: $ git grep -l PHYS_ADDR_T_64BIT arch | grep Kconfig arch/arc/Kconfig arch/arm/mm/Kconfig arch/mips/Kconfig arch/powerpc/platforms/Kconfig.cputype arch/x86/Kconfig arch/arc has a CONFIG_ARC_HAS_PAE40 option arch/riscv has 34-bit addressing in rv32 mode arch/mips has up to 40 bits with mips32r3 XPA, but I don't know what supports that arch/powerpc has this: config PHYS_64BIT bool 'Large physical address support' if E500 || PPC_86xx depends on (44x || E500 || PPC_86xx) && !PPC_83xx && !PPC_82xx Apparently all three (4xx, e500v2, mpc86xx/e600) do 36-bit physical addressing, but each one has a different page table format. Microblaze has physical address extensions, but neither those nor 64-bit mode have so far made it into the kernel. To be on the safe side, we could provoke a compile-time error when CONFIG_PHYS_ADDR_T_64BIT is set on a 32-bit architecture, but MAX_POSSIBLE_PHYSMEM_BITS is not set. > That's what x86 does: > > $ git grep -w MAX_POSSIBLE_PHYSMEM_BITS arch/ > arch/x86/include/asm/pgtable-3level_types.h:#define MAX_POSSIBLE_PHYSMEM_BITS 36 Doesn't x86 also support a 40-bit addressing mode? I suppose those machines that actually used it are long gone. > arch/x86/include/asm/pgtable_64_types.h:#define MAX_POSSIBLE_PHYSMEM_BITS 52 > > It seems that actual numbers would be 36 for !LPAE and 40 for LPAE, but > I'm not sure about that. Close enough, yes. The 36-bit addressing is on !LPAE is only used for early static mappings, so I think we can pretend it's always 32-bit. I checked the ARMv8 reference, and it says that ARMv8-Aarch32 actually supports 40 bit physical addressing both with non-LPAE superpages (short descriptor format) and LPAE (long descriptor format), but Linux only does 36-bit addressing on superpages as specified for ARMv6/ARMv7 short descriptors. Arnd