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Wed, 18 Oct 2023 13:28:59 -0700 (PDT) Received: from 348282803490 named unknown by gmailapi.google.com with HTTPREST; Wed, 18 Oct 2023 13:28:58 -0700 From: Emil Renner Berthing In-Reply-To: References: <20231017-module_relocations-v4-0-937f5ef316f0@rivosinc.com> <20231017-module_relocations-v4-1-937f5ef316f0@rivosinc.com> Mime-Version: 1.0 Date: Wed, 18 Oct 2023 13:28:58 -0700 Message-ID: Subject: Re: [PATCH v4 1/2] riscv: Add remaining module relocations To: Charlie Jenkins , Emil Renner Berthing Cc: linux-riscv@lists.infradead.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org, Eric Biederman , Kees Cook , Paul Walmsley , Palmer Dabbelt , Albert Ou Content-Type: text/plain; charset="UTF-8" X-Rspam-User: X-Rspamd-Server: rspam12 X-Rspamd-Queue-Id: B0C4414000C X-Stat-Signature: gedegerjo8xhwe6ba9mnmgrh9oyh7mrb X-HE-Tag: 1697660942-252626 X-HE-Meta: U2FsdGVkX1+czoDD8+TO/Pnd5t2bOJ7X7gjUHWZv2EBsIeezaoPJ1AGam54bSY/D9JWC7pM+1TeccRaa5b8EuPbdjPRdFjlXEC4VCEyKiKaXRdw+dtyXeOYRryiQ7WPR30cpzGVMKx8t9bm5JwHKy0q4FmlTApJ4X4m2UAHRk0T87CjQt8BdiDvs2l2CfAfi8yB0dxvuaYag7FgrhFqDMgN/KHgH19fstac6uf97Q7T+8kzB5ZWSfbT1Neh7GmEVMS6v0byub7S6JFZyRb1XUO2KUqZDPsiL9jyhsneD1n4BUEO6/2gbs+RfJO5LR0bItwy0/B60Wg0IUWnCTxxUsjDk6U7mKoZHKLieZ+RcxFZMwEdr5DepJGkkA8Q+H9KqFvcadCrvjvyd33nk7TKyxuOneu9rVtg8WtnlRRgkIq7Ex+ev6J3cF3YNwnDbZncCzbA+gpg9AhgXdaCVMLEC9D6odtDIsaNUBLrlsQTkIRNgAisR/C222CnFiLI28vFkEJ2xAhPa1OZ6p6ZsIz399dv6UfbI0aZYA+wcqIcLALlCsstAAjvgSNizlAnjdPUW1u98skjy93yflxFytXx1wj2KpO4dYUwVDLtlloOc7Q5ZGxbEeDD4a+mkJXNbUbCUE8M0YXYDvnGw/Y6h9S2u7Qvzmr0aPqYNn0hSnGktwfFS/9nyTFUTZV8RLlxyCOl6nns3rMtFiWyf5RSTEpNPfR3bn/pw4Vwc6XVqIgbG6eGLwcKsuO2z5OwTgxL+CexgeLuNMZsR/igbI7t98vEWuD0Ny8XMTfnYJydQtF3Ljz61rdheSDXtTZR+DkcvCYFkCM15mGHAPzgTHIX9tiStDt1nyKHnIjbBh45TcJ/hQSUSkZGxpDnCAUuFrLJxPkFHUzCeasndCc6CmDuVeNUkQ0w2L05IgqNPrtpJL2Lz8mTFUpAf3fMP0rP6Trv2mVmCHKzOHhqae4YF0euhhyP gRHYMUv1 OLgKlQRjCQjC8NnzorrBGCRbBxpQhaSZSSv3LwJnuHp8f6QmFi0udel9GJn5snDb4FuZg5SXONttQV4WTO2m1jZ59Tr5otrq6V7R7C1Vzn3BXWtTBd0kr0nxaVNkX9r9QotTf/l7eJ3zVKl9TdUX2Fxu8Hr/wskxbPn24mLzv/Bw3Ax9gnLhsQ+5NuNmJPRf0edCbrtjj4oJIIkrDvm50tr/soA3hD+Rn9WN2DYbmskpdlFaD1x00Cnrm6wY9jQwjnvAIJSin4GFZpieCfEBnJrb1lTGAmZDCE/Z5ESFG9706XSwHnOvmYsaV+XCeSBH9zgOzsz3ffuMc8z8A7MGv9avaXI9zq2lR5NkC0FJsav0NSjvDA2/T2UHC8NKyspcU17v9It3xmeG2cIH0phxB4ML05JqBLoA8MLXwdF3LiVgIGcuEld8EwGkFf9UjXQesvg3AiInVtaO7/9o= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Charlie Jenkins wrote: > On Wed, Oct 18, 2023 at 11:38:39AM -0700, Emil Renner Berthing wrote: > > Charlie Jenkins wrote: > > > On Wed, Oct 18, 2023 at 05:17:44AM -0700, Emil Renner Berthing wrote: > > > > Charlie Jenkins wrote: > > > > > Add all final module relocations and add error logs explaining the ones > > > > > that are not supported. > > > > > > > > > > Signed-off-by: Charlie Jenkins > > > > > --- > > > > > arch/riscv/include/uapi/asm/elf.h | 5 +- > > > > > arch/riscv/kernel/module.c | 207 +++++++++++++++++++++++++++++++++----- > > > > > 2 files changed, 186 insertions(+), 26 deletions(-) > > > > > > > > > > diff --git a/arch/riscv/include/uapi/asm/elf.h b/arch/riscv/include/uapi/asm/elf.h > > > > > index d696d6610231..11a71b8533d5 100644 > > > > > --- a/arch/riscv/include/uapi/asm/elf.h > > > > > +++ b/arch/riscv/include/uapi/asm/elf.h > > > > > @@ -49,6 +49,7 @@ typedef union __riscv_fp_state elf_fpregset_t; > > > > > #define R_RISCV_TLS_DTPREL64 9 > > > > > #define R_RISCV_TLS_TPREL32 10 > > > > > #define R_RISCV_TLS_TPREL64 11 > > > > > +#define R_RISCV_IRELATIVE 58 > > > > > > > > > > /* Relocation types not used by the dynamic linker */ > > > > > #define R_RISCV_BRANCH 16 > > > > > @@ -81,7 +82,6 @@ typedef union __riscv_fp_state elf_fpregset_t; > > > > > #define R_RISCV_ALIGN 43 > > > > > #define R_RISCV_RVC_BRANCH 44 > > > > > #define R_RISCV_RVC_JUMP 45 > > > > > -#define R_RISCV_LUI 46 > > > > > #define R_RISCV_GPREL_I 47 > > > > > #define R_RISCV_GPREL_S 48 > > > > > #define R_RISCV_TPREL_I 49 > > > > > @@ -93,6 +93,9 @@ typedef union __riscv_fp_state elf_fpregset_t; > > > > > #define R_RISCV_SET16 55 > > > > > #define R_RISCV_SET32 56 > > > > > #define R_RISCV_32_PCREL 57 > > > > > +#define R_RISCV_PLT32 59 > > > > > +#define R_RISCV_SET_ULEB128 60 > > > > > +#define R_RISCV_SUB_ULEB128 61 > > > > > > > > > > > > > > > #endif /* _UAPI_ASM_RISCV_ELF_H */ > > > > > diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c > > > > > index 7c651d55fcbd..e860726352ac 100644 > > > > > --- a/arch/riscv/kernel/module.c > > > > > +++ b/arch/riscv/kernel/module.c > > > > > @@ -7,6 +7,7 @@ > > > > > #include > > > > > #include > > > > > #include > > > > > +#include > > > > > #include > > > > > #include > > > > > #include > > > > > @@ -268,6 +269,12 @@ static int apply_r_riscv_align_rela(struct module *me, u32 *location, > > > > > return -EINVAL; > > > > > } > > > > > > > > > > +static int apply_r_riscv_add8_rela(struct module *me, u32 *location, Elf_Addr v) > > > > > +{ > > > > > + *(u8 *)location += (u8)v; > > > > > + return 0; > > > > > +} > > > > > + > > > > > static int apply_r_riscv_add16_rela(struct module *me, u32 *location, > > > > > Elf_Addr v) > > > > > { > > > > > @@ -289,6 +296,12 @@ static int apply_r_riscv_add64_rela(struct module *me, u32 *location, > > > > > return 0; > > > > > } > > > > > > > > > > +static int apply_r_riscv_sub8_rela(struct module *me, u32 *location, Elf_Addr v) > > > > > +{ > > > > > + *(u8 *)location -= (u8)v; > > > > > + return 0; > > > > > +} > > > > > + > > > > > static int apply_r_riscv_sub16_rela(struct module *me, u32 *location, > > > > > Elf_Addr v) > > > > > { > > > > > @@ -310,31 +323,149 @@ static int apply_r_riscv_sub64_rela(struct module *me, u32 *location, > > > > > return 0; > > > > > } > > > > > > > > > > -static int (*reloc_handlers_rela[]) (struct module *me, u32 *location, > > > > > - Elf_Addr v) = { > > > > > - [R_RISCV_32] = apply_r_riscv_32_rela, > > > > > - [R_RISCV_64] = apply_r_riscv_64_rela, > > > > > - [R_RISCV_BRANCH] = apply_r_riscv_branch_rela, > > > > > - [R_RISCV_JAL] = apply_r_riscv_jal_rela, > > > > > - [R_RISCV_RVC_BRANCH] = apply_r_riscv_rvc_branch_rela, > > > > > - [R_RISCV_RVC_JUMP] = apply_r_riscv_rvc_jump_rela, > > > > > - [R_RISCV_PCREL_HI20] = apply_r_riscv_pcrel_hi20_rela, > > > > > - [R_RISCV_PCREL_LO12_I] = apply_r_riscv_pcrel_lo12_i_rela, > > > > > - [R_RISCV_PCREL_LO12_S] = apply_r_riscv_pcrel_lo12_s_rela, > > > > > - [R_RISCV_HI20] = apply_r_riscv_hi20_rela, > > > > > - [R_RISCV_LO12_I] = apply_r_riscv_lo12_i_rela, > > > > > - [R_RISCV_LO12_S] = apply_r_riscv_lo12_s_rela, > > > > > - [R_RISCV_GOT_HI20] = apply_r_riscv_got_hi20_rela, > > > > > - [R_RISCV_CALL_PLT] = apply_r_riscv_call_plt_rela, > > > > > - [R_RISCV_CALL] = apply_r_riscv_call_rela, > > > > > - [R_RISCV_RELAX] = apply_r_riscv_relax_rela, > > > > > - [R_RISCV_ALIGN] = apply_r_riscv_align_rela, > > > > > - [R_RISCV_ADD16] = apply_r_riscv_add16_rela, > > > > > - [R_RISCV_ADD32] = apply_r_riscv_add32_rela, > > > > > - [R_RISCV_ADD64] = apply_r_riscv_add64_rela, > > > > > - [R_RISCV_SUB16] = apply_r_riscv_sub16_rela, > > > > > - [R_RISCV_SUB32] = apply_r_riscv_sub32_rela, > > > > > - [R_RISCV_SUB64] = apply_r_riscv_sub64_rela, > > > > > +static int dynamic_linking_not_supported(struct module *me, u32 *location, > > > > > + Elf_Addr v) > > > > > +{ > > > > > + pr_err("%s: Dynamic linking not supported in kernel modules PC = %p\n", > > > > > + me->name, location); > > > > > + return -EINVAL; > > > > > +} > > > > > + > > > > > +static int tls_not_supported(struct module *me, u32 *location, Elf_Addr v) > > > > > +{ > > > > > + pr_err("%s: Thread local storage not supported in kernel modules PC = %p\n", > > > > > + me->name, location); > > > > > + return -EINVAL; > > > > > +} > > > > > + > > > > > +static int apply_r_riscv_sub6_rela(struct module *me, u32 *location, Elf_Addr v) > > > > > +{ > > > > > + *(u8 *)location = (*location - ((u8)v & 0x3F)) & 0x3F; > > > > > + return 0; > > > > > +} > > > > > + > > > > > +static int apply_r_riscv_set6_rela(struct module *me, u32 *location, Elf_Addr v) > > > > > +{ > > > > > + *(u8 *)location = (*(u8 *)location & 0xc0) | ((u8)v & 0x3F); > > > > > + return 0; > > > > > +} > > > > > + > > > > > +static int apply_r_riscv_set8_rela(struct module *me, u32 *location, Elf_Addr v) > > > > > +{ > > > > > + *(u8 *)location = (u8)v; > > > > > + return 0; > > > > > +} > > > > > + > > > > > +static int apply_r_riscv_set16_rela(struct module *me, u32 *location, > > > > > + Elf_Addr v) > > > > > +{ > > > > > + *(u16 *)location = (u16)v; > > > > > + return 0; > > > > > +} > > > > > + > > > > > +static int apply_r_riscv_set32_rela(struct module *me, u32 *location, > > > > > + Elf_Addr v) > > > > > +{ > > > > > + *(u32 *)location = (u32)v; > > > > > + return 0; > > > > > +} > > > > > + > > > > > +static int apply_r_riscv_32_pcrel_rela(struct module *me, u32 *location, > > > > > + Elf_Addr v) > > > > > +{ > > > > > + *(u32 *)location = (u32)v; > > > > > + return 0; > > > > > +} > > > > > + > > > > > +static int apply_r_riscv_plt32_rela(struct module *me, u32 *location, > > > > > + Elf_Addr v) > > > > > +{ > > > > > + *(u32 *)location = (u32)v; > > > > > + return 0; > > > > > +} > > > > > + > > > > > +static int apply_r_riscv_set_uleb128(struct module *me, u32 *location, Elf_Addr v) > > > > > +{ > > > > > + /* > > > > > + * Relocation is only performed if R_RISCV_SET_ULEB128 is followed by > > > > > + * R_RISCV_SUB_ULEB128 so do computation there > > > > > + */ > > > > > + return 0; > > > > > +} > > > > > + > > > > > +static int apply_r_riscv_sub_uleb128(struct module *me, u32 *location, Elf_Addr v) > > > > > +{ > > > > > + if (v >= 128) { > > > > > + pr_err("%s: uleb128 must be in [0, 127] (not %ld) at PC = %p\n", > > > > > + me->name, (unsigned long)v, location); > > > > > + return -EINVAL; > > > > > + } > > > > > + > > > > > + *location = v; > > > > > + return 0; > > > > > +} > > > > > + > > > > > +/* > > > > > + * Relocations defined in the riscv-elf-psabi-doc. > > > > > + * This handles static linking only. > > > > > + */ > > > > > +static int (*reloc_handlers_rela[])(struct module *me, u32 *location, > > > > > + Elf_Addr v) = { > > > > > + [R_RISCV_32] = apply_r_riscv_32_rela, > > > > > + [R_RISCV_64] = apply_r_riscv_64_rela, > > > > > + [R_RISCV_RELATIVE] = dynamic_linking_not_supported, > > > > > + [R_RISCV_COPY] = dynamic_linking_not_supported, > > > > > + [R_RISCV_JUMP_SLOT] = dynamic_linking_not_supported, > > > > > + [R_RISCV_TLS_DTPMOD32] = dynamic_linking_not_supported, > > > > > + [R_RISCV_TLS_DTPMOD64] = dynamic_linking_not_supported, > > > > > + [R_RISCV_TLS_DTPREL32] = dynamic_linking_not_supported, > > > > > + [R_RISCV_TLS_DTPREL64] = dynamic_linking_not_supported, > > > > > + [R_RISCV_TLS_TPREL32] = dynamic_linking_not_supported, > > > > > + [R_RISCV_TLS_TPREL64] = dynamic_linking_not_supported, > > > > > + /* 12-15 undefined */ > > > > > + [R_RISCV_BRANCH] = apply_r_riscv_branch_rela, > > > > > + [R_RISCV_JAL] = apply_r_riscv_jal_rela, > > > > > + [R_RISCV_CALL] = apply_r_riscv_call_rela, > > > > > + [R_RISCV_CALL_PLT] = apply_r_riscv_call_plt_rela, > > > > > + [R_RISCV_GOT_HI20] = apply_r_riscv_got_hi20_rela, > > > > > + [R_RISCV_TLS_GOT_HI20] = tls_not_supported, > > > > > + [R_RISCV_TLS_GD_HI20] = tls_not_supported, > > > > > + [R_RISCV_PCREL_HI20] = apply_r_riscv_pcrel_hi20_rela, > > > > > + [R_RISCV_PCREL_LO12_I] = apply_r_riscv_pcrel_lo12_i_rela, > > > > > + [R_RISCV_PCREL_LO12_S] = apply_r_riscv_pcrel_lo12_s_rela, > > > > > + [R_RISCV_HI20] = apply_r_riscv_hi20_rela, > > > > > + [R_RISCV_LO12_I] = apply_r_riscv_lo12_i_rela, > > > > > + [R_RISCV_LO12_S] = apply_r_riscv_lo12_s_rela, > > > > > + [R_RISCV_TPREL_HI20] = tls_not_supported, > > > > > + [R_RISCV_TPREL_LO12_I] = tls_not_supported, > > > > > + [R_RISCV_TPREL_LO12_S] = tls_not_supported, > > > > > + [R_RISCV_TPREL_ADD] = tls_not_supported, > > > > > + [R_RISCV_ADD8] = apply_r_riscv_add8_rela, > > > > > + [R_RISCV_ADD16] = apply_r_riscv_add16_rela, > > > > > + [R_RISCV_ADD32] = apply_r_riscv_add32_rela, > > > > > + [R_RISCV_ADD64] = apply_r_riscv_add64_rela, > > > > > + [R_RISCV_SUB8] = apply_r_riscv_sub8_rela, > > > > > + [R_RISCV_SUB16] = apply_r_riscv_sub16_rela, > > > > > + [R_RISCV_SUB32] = apply_r_riscv_sub32_rela, > > > > > + [R_RISCV_SUB64] = apply_r_riscv_sub64_rela, > > > > > + /* 41-42 reserved for future standard use */ > > > > > + [R_RISCV_ALIGN] = apply_r_riscv_align_rela, > > > > > + [R_RISCV_RVC_BRANCH] = apply_r_riscv_rvc_branch_rela, > > > > > + [R_RISCV_RVC_JUMP] = apply_r_riscv_rvc_jump_rela, > > > > > + /* 46-50 reserved for future standard use */ > > > > > + [R_RISCV_RELAX] = apply_r_riscv_relax_rela, > > > > > + [R_RISCV_SUB6] = apply_r_riscv_sub6_rela, > > > > > + [R_RISCV_SET6] = apply_r_riscv_set6_rela, > > > > > + [R_RISCV_SET8] = apply_r_riscv_set8_rela, > > > > > + [R_RISCV_SET16] = apply_r_riscv_set16_rela, > > > > > + [R_RISCV_SET32] = apply_r_riscv_set32_rela, > > > > > + [R_RISCV_32_PCREL] = apply_r_riscv_32_pcrel_rela, > > > > > + [R_RISCV_IRELATIVE] = dynamic_linking_not_supported, > > > > > + [R_RISCV_PLT32] = apply_r_riscv_plt32_rela, > > > > > + [R_RISCV_SET_ULEB128] = apply_r_riscv_set_uleb128, > > > > > + [R_RISCV_SUB_ULEB128] = apply_r_riscv_sub_uleb128, > > > > > + /* 62-191 reserved for future standard use */ > > > > > + /* 192-255 nonstandard ABI extensions */ > > > > > }; > > > > > > > > Hi Charlie, > > > > > > > > This is not a critique of this patch, but all these callbacks take a > > > > u32 *location and > > > > because of the compressed instructions this pointer may not be > > > > aligned, so a lot of > > > > the callbacks end up doing unaligned access which may fault to an > > > > M-mode handler on > > > > some platforms. > > > > > > > > I once sent a patch to fix this: > > > > https://lore.kernel.org/linux-riscv/20220224152456.493365-2-kernel@esmil.dk/ > > > > > > > > Maybe that's something you want to look into while touching this code anyway. > > > > > > > > /Emil > > > > > > Oh nice, I will pick up that patch and change the "native-endian" > > > wording to be "little-endian" in the commit. > > > > Great, thanks. You'll probably also want the reads to be wrapped in > > le16_to_cpu() and similar when writing now that it's decided that the parcels > > are always in little-endian byteorder. > > > > /Emil > > I believe that le16_to_cpu() is only needed when instructions are being modified, and > the relocations that only touch data can be left alone. Is this correct? Yes, that sounds right to me. I only meant in the riscv_insn_rmw() function of my patch and the callbacks modifying a compressed instruction, but I haven't gone through all the other reloc types to check if they have a set endianess. /Emil