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[209.85.221.54]) by smtp.gmail.com with ESMTPSA id ht15sm1649840ejc.122.2022.01.09.12.00.48 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 09 Jan 2022 12:00:49 -0800 (PST) Received: by mail-wr1-f54.google.com with SMTP id s1so22927025wra.6 for ; Sun, 09 Jan 2022 12:00:48 -0800 (PST) X-Received: by 2002:adf:eeca:: with SMTP id a10mr17443019wrp.274.1641758448174; Sun, 09 Jan 2022 12:00:48 -0800 (PST) MIME-Version: 1.0 References: <7c9c388c388df8e88bb5d14828053ac0cb11cf69.1641659630.git.luto@kernel.org> <739A3109-04DD-4BA5-A02B-52EE30E820AE@gmail.com> <355c148c-06a8-4e15-a77b-0ea2e22bf708@www.fastmail.com> In-Reply-To: <355c148c-06a8-4e15-a77b-0ea2e22bf708@www.fastmail.com> From: Linus Torvalds Date: Sun, 9 Jan 2022 12:00:32 -0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 16/23] sched: Use lightweight hazard pointers to grab lazy mms To: Andy Lutomirski Cc: Nadav Amit , Andrew Morton , Linux-MM , Nicholas Piggin , Anton Blanchard , Benjamin Herrenschmidt , Paul Mackerras , Randy Dunlap , linux-arch , "the arch/x86 maintainers" , Rik van Riel , Dave Hansen , "Peter Zijlstra (Intel)" , Mathieu Desnoyers Content-Type: text/plain; charset="UTF-8" X-Rspamd-Server: rspam07 X-Rspamd-Queue-Id: 3384316000D X-Stat-Signature: if6hscgiexh9jrsmouxk5p9jz5b8r8ow Authentication-Results: imf08.hostedemail.com; dkim=pass header.d=linux-foundation.org header.s=google header.b="IcrK3Xa/"; dmarc=none; spf=pass (imf08.hostedemail.com: domain of torvalds@linuxfoundation.org designates 209.85.208.44 as permitted sender) smtp.mailfrom=torvalds@linuxfoundation.org X-HE-Tag: 1641758452-833112 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On Sun, Jan 9, 2022 at 11:53 AM Andy Lutomirski wrote: > > My original PCID series actually did remove lazy TLB on x86. I don't > remember why, but people objected. The issue isn't the limited PCID > space -- IIRC it's just that MOV CR3 is slooooow. If we get rid of > lazy TLB on x86, then we are writing CR3 twice on even a very short > idle. That adds maybe 1k cycles, which isn't great. Yeah, my gut feel is that lazy-TLB almost certainly makes sense on x86. And the grab/mmput overhead and associated cacheline ping-pong is (I think) something we could just get rid of on x86 due to the IPI model. There are probably other costs to lazy TLB, and I can imagine that there are other maintenance costs, but yes, cr3 moves have always been expensive on x86 even aside from the actual TLB switch. But I could easily imagine the situation being different on arm64, for example. But numbers beat "gut feel" and "easily imagine" every time. So it would be kind of nice to have that ... Linus