From: Alexandre Ghiti <alexghiti@rivosinc.com>
To: Samuel Holland <samuel.holland@sifive.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-mm@kvack.org
Subject: Re: [PATCH v4 03/12] riscv: mm: Broadcast kernel TLB flushes only when needed
Date: Thu, 4 Jan 2024 13:15:06 +0100 [thread overview]
Message-ID: <CAHVXubjv58osbweO8AtyubLq=Zd7GW5aaeO6qFdb-QLTKrzT4g@mail.gmail.com> (raw)
In-Reply-To: <20240102220134.3229156-4-samuel.holland@sifive.com>
On Tue, Jan 2, 2024 at 11:01 PM Samuel Holland
<samuel.holland@sifive.com> wrote:
>
> __flush_tlb_range() avoids broadcasting TLB flushes when an mm context
> is only active on the local CPU. Apply this same optimization to TLB
> flushes of kernel memory when only one CPU is online. This check can be
> constant-folded when SMP is disabled.
>
> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
> ---
>
> Changes in v4:
> - New patch for v4
>
> arch/riscv/mm/tlbflush.c | 17 ++++++-----------
> 1 file changed, 6 insertions(+), 11 deletions(-)
>
> diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c
> index 09b03bf71e6a..2f18fe6fc4f3 100644
> --- a/arch/riscv/mm/tlbflush.c
> +++ b/arch/riscv/mm/tlbflush.c
> @@ -98,27 +98,23 @@ static void __flush_tlb_range(struct mm_struct *mm, unsigned long start,
> {
> const struct cpumask *cmask;
> unsigned long asid = FLUSH_TLB_NO_ASID;
> - bool broadcast;
> + unsigned int cpu;
>
> if (mm) {
> - unsigned int cpuid;
> -
> cmask = mm_cpumask(mm);
> if (cpumask_empty(cmask))
> return;
>
> - cpuid = get_cpu();
> - /* check if the tlbflush needs to be sent to other CPUs */
> - broadcast = cpumask_any_but(cmask, cpuid) < nr_cpu_ids;
> -
> if (static_branch_unlikely(&use_asid_allocator))
> asid = atomic_long_read(&mm->context.id) & asid_mask;
> } else {
> cmask = cpu_online_mask;
> - broadcast = true;
> }
>
> - if (!broadcast) {
> + cpu = get_cpu();
> +
> + /* Check if the TLB flush needs to be sent to other CPUs. */
> + if (cpumask_any_but(cmask, cpu) >= nr_cpu_ids) {
> local_flush_tlb_range_asid(start, size, stride, asid);
> } else if (riscv_use_sbi_for_rfence()) {
> sbi_remote_sfence_vma_asid(cmask, start, size, asid);
> @@ -132,8 +128,7 @@ static void __flush_tlb_range(struct mm_struct *mm, unsigned long start,
> on_each_cpu_mask(cmask, __ipi_flush_tlb_range_asid, &ftd, 1);
> }
>
> - if (mm)
> - put_cpu();
> + put_cpu();
> }
>
> void flush_tlb_mm(struct mm_struct *mm)
> --
> 2.42.0
>
You can add:
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Thanks,
Alex
next prev parent reply other threads:[~2024-01-04 12:15 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-02 22:00 [PATCH v4 00/12] riscv: ASID-related and UP-related TLB flush enhancements Samuel Holland
2024-01-02 22:00 ` [PATCH v4 01/12] riscv: Flush the instruction cache during SMP bringup Samuel Holland
2024-01-04 11:58 ` Alexandre Ghiti
2024-01-02 22:00 ` [PATCH v4 02/12] riscv: Use IPIs for remote cache/TLB flushes by default Samuel Holland
2024-01-04 12:09 ` Alexandre Ghiti
2024-01-02 22:00 ` [PATCH v4 03/12] riscv: mm: Broadcast kernel TLB flushes only when needed Samuel Holland
2024-01-04 12:15 ` Alexandre Ghiti [this message]
2024-01-02 22:00 ` [PATCH v4 04/12] riscv: Only send remote fences when some other CPU is online Samuel Holland
2024-01-03 14:57 ` Jisheng Zhang
2024-01-03 15:04 ` Jisheng Zhang
2024-01-04 12:33 ` Alexandre Ghiti
2024-01-04 15:33 ` Samuel Holland
2024-01-02 22:00 ` [PATCH v4 05/12] riscv: mm: Combine the SMP and UP TLB flush code Samuel Holland
2024-01-04 12:36 ` Alexandre Ghiti
2024-01-02 22:00 ` [PATCH v4 06/12] riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma Samuel Holland
2024-01-02 22:00 ` [PATCH v4 07/12] riscv: Avoid TLB flush loops when affected by SiFive CIP-1200 Samuel Holland
2024-01-02 22:00 ` [PATCH v4 08/12] riscv: mm: Introduce cntx2asid/cntx2version helper macros Samuel Holland
2024-01-04 12:39 ` Alexandre Ghiti
2024-01-04 15:42 ` Samuel Holland
2024-01-02 22:00 ` [PATCH v4 09/12] riscv: mm: Use a fixed layout for the MM context ID Samuel Holland
2024-01-04 12:42 ` Alexandre Ghiti
2024-01-02 22:00 ` [PATCH v4 10/12] riscv: mm: Make asid_bits a local variable Samuel Holland
2024-01-03 15:00 ` Jisheng Zhang
2024-01-04 15:49 ` Samuel Holland
2024-01-04 12:47 ` Alexandre Ghiti
2024-01-02 22:00 ` [PATCH v4 11/12] riscv: mm: Preserve global TLB entries when switching contexts Samuel Holland
2024-01-04 12:55 ` Alexandre Ghiti
2024-01-02 22:00 ` [PATCH v4 12/12] riscv: mm: Always use an ASID to flush mm contexts Samuel Holland
2024-01-03 15:02 ` Jisheng Zhang
2024-01-04 15:50 ` Samuel Holland
2024-01-04 13:01 ` Alexandre Ghiti
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='CAHVXubjv58osbweO8AtyubLq=Zd7GW5aaeO6qFdb-QLTKrzT4g@mail.gmail.com' \
--to=alexghiti@rivosinc.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mm@kvack.org \
--cc=linux-riscv@lists.infradead.org \
--cc=palmer@dabbelt.com \
--cc=samuel.holland@sifive.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox