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Wed, 13 Sep 2023 01:32:24 -0700 (PDT) MIME-Version: 1.0 References: <20230911131224.61924-1-alexghiti@rivosinc.com> <20230911131224.61924-5-alexghiti@rivosinc.com> In-Reply-To: From: Alexandre Ghiti Date: Wed, 13 Sep 2023 10:32:13 +0200 Message-ID: Subject: Re: [PATCH v4 4/4] riscv: Improve flush_tlb_kernel_range() To: "Lad, Prabhakar" Cc: Will Deacon , "Aneesh Kumar K . V" , Andrew Morton , Nick Piggin , Peter Zijlstra , Mayuresh Chitale , Vincent Chen , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-arch@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Samuel Holland , Andrew Jones Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Rspam-User: X-Stat-Signature: 4pmyt1dxsuj6ompbby8ds7476yqjd8o9 X-Rspamd-Server: rspam07 X-Rspamd-Queue-Id: 2C3482000D X-HE-Tag: 1694593945-437299 X-HE-Meta: U2FsdGVkX18HRWnTQpWOrU89uRpS1dLsCQT8D35HpZzGKUhrwzbmneHVuKcHAAHlCCZo8buyZupPXH2yyzXpUvgB3bJcZH3oqTvpg7OoWS0PxTRtrfQ5U9R+IYa68gySyVeMcqzI1rts3QS6CPKManTcy2fcPZZI+bHMSzN2+Q/jTbewKgvGm7oOmEehk2jbslV4fq4N2u36ewohqcB+tFGcS5RjoJP3bYIzBGuDHgjgF/uOCCSDg5NHNx7QXnrhH9WKkgbHWS2g68L1WeszVeeXuo3UqaWgpFnKDojW9vB0FqnX9kojm1CCGMvIAb+g8h1S9Y8DPe09LW+jsiwlZ4+0SJDtPRDFEU3En+QnE9znmyrl6qYJP4/tslLFSLqyJ2pHvb/raETWJpsY5ub4PYBJGo43Pev/jBfQkA+57oJ4+skWwKFDLzF+VQoFHduyBf9wcHqriU1pR29GQtYGVA1DbfKYO8ESXBtaBMdFre3GH/fBmwwGr0IQfkZpfNxw0raw7FcV8ug/bxMGEo8GbsOvSO4gvU6nqaF+u3GxmiKtoQ6uXNwkLz5Efo3jnYus0t5zGTEemNwwRImd5oEoZUozx2pPvRXMB6iVMj0ObhcewSNgehKVP9YsAtqXeDhsPT+R/ChY7ydzOrrfidxooPB8ckMto7kB+Y5E5NT8oYXfWePRHAknFm0yxiOyqP5FjVM8Ben1chnICMnUddOXAKbeC4IfVHJmRrb8xqxbHCZK8/jdCKLSeLTOFgt+4EQIqaJl61jnN2lU632PUf7D8856I9ejZ8jIE30AX4XAXYGPDH/So3HQep5p6Lj5YHyWUthoKNwdaqaBO/M33z6dxFWt+OZ+S3NTLkAbiJc08x39NPioV8pRf6KFvoy7tMTuSuugLKyyu/i7nosrgiuFE1Nm6u0KHeXT9kluCoHIntADjV4wkdAHcgyMb9NCakIiKY+5Vp1rDCCEADsR5nS 7hHB0Aca GPy0/942tJRrB1Lq264mX+VVjbaA97bFIYRFdFkqYvi2ub/CYHrHrIkfGJofKS7oZc+KKtUOA0Zt5fOH+h60SO7UVNDY5OjoJCYp/vpPduuTT2uP5bVbwAiHJD7blFh+D6AAN2qC76TbrpXHu8Ybt6h8fJdPi5rn/y9CL6KCVE+TW8FTGTHH0yrr9w3GqPX3dTzQ3adH6hzar11caPB0PTbdfeF0HvEf7/gXkDwIHmo5xk8n+co86XmriEmjhNxix+FyLKmH8Sa3b8Jhe3JXGjW/oi3OnqIwr2RduQoCSmaIJ/vkHh8ZcH1bFLKHEzQ5FYGrMUFZ628uboMgrMm6kPRypdCmFYjFkI+zLh1ZgWhfo5poD5uq4hWPQENteQRTYHirXy5gpWxzp38ivnjch3itNIYMBwH8dR/CIx3T7Ne3X3hnuDwtH7O321fSffetf48g3drK+2T4jbB9xdLM0gL7Q6RA/A3s5gnq87DNQT1GY7N42xPULzVlz1nCNrjy1cQoQtSSsK05iFiGywNVPQhMXBw== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On Wed, Sep 13, 2023 at 10:24=E2=80=AFAM Lad, Prabhakar wrote: > > Hi Alexandre, > > On Wed, Sep 13, 2023 at 9:04=E2=80=AFAM Alexandre Ghiti wrote: > > > > @Lad, Prabhakar Any chance you give a try to this new patchset? So > > that we make sure Samuel found your issue :) > > > I have given the patches a try and not seen the module load failures > as seen previously. I have some rigorous tests which test the complete > platform. I'm just waiting for it to complete before I give Tested by. > Awesome, thanks for the update! Well done @Samuel Holland > Cheers, > Prabhakar > > > On Mon, Sep 11, 2023 at 3:16=E2=80=AFPM Alexandre Ghiti wrote: > > > > > > This function used to simply flush the whole tlb of all harts, be mor= e > > > subtile and try to only flush the range. > > > > > > The problem is that we can only use PAGE_SIZE as stride since we don'= t know > > > the size of the underlying mapping and then this function will be imp= roved > > > only if the size of the region to flush is < threshold * PAGE_SIZE. > > > > > > Signed-off-by: Alexandre Ghiti > > > Reviewed-by: Andrew Jones > > > --- > > > arch/riscv/include/asm/tlbflush.h | 11 ++++++----- > > > arch/riscv/mm/tlbflush.c | 33 ++++++++++++++++++++++-------= -- > > > 2 files changed, 30 insertions(+), 14 deletions(-) > > > > > > diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/a= sm/tlbflush.h > > > index 170a49c531c6..8f3418c5f172 100644 > > > --- a/arch/riscv/include/asm/tlbflush.h > > > +++ b/arch/riscv/include/asm/tlbflush.h > > > @@ -40,6 +40,7 @@ void flush_tlb_mm_range(struct mm_struct *mm, unsig= ned long start, > > > void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr); > > > void flush_tlb_range(struct vm_area_struct *vma, unsigned long start= , > > > unsigned long end); > > > +void flush_tlb_kernel_range(unsigned long start, unsigned long end); > > > #ifdef CONFIG_TRANSPARENT_HUGEPAGE > > > #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE > > > void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long s= tart, > > > @@ -56,15 +57,15 @@ static inline void flush_tlb_range(struct vm_area= _struct *vma, > > > local_flush_tlb_all(); > > > } > > > > > > -#define flush_tlb_mm(mm) flush_tlb_all() > > > -#define flush_tlb_mm_range(mm, start, end, page_size) flush_tlb_all(= ) > > > -#endif /* !CONFIG_SMP || !CONFIG_MMU */ > > > - > > > /* Flush a range of kernel pages */ > > > static inline void flush_tlb_kernel_range(unsigned long start, > > > unsigned long end) > > > { > > > - flush_tlb_all(); > > > + local_flush_tlb_all(); > > > } > > > > > > +#define flush_tlb_mm(mm) flush_tlb_all() > > > +#define flush_tlb_mm_range(mm, start, end, page_size) flush_tlb_all(= ) > > > +#endif /* !CONFIG_SMP || !CONFIG_MMU */ > > > + > > > #endif /* _ASM_RISCV_TLBFLUSH_H */ > > > diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c > > > index 2c1136d73411..28cd8539b575 100644 > > > --- a/arch/riscv/mm/tlbflush.c > > > +++ b/arch/riscv/mm/tlbflush.c > > > @@ -97,19 +97,27 @@ static void __flush_tlb_range(struct mm_struct *m= m, unsigned long start, > > > unsigned long size, unsigned long strid= e) > > > { > > > struct flush_tlb_range_data ftd; > > > - struct cpumask *cmask =3D mm_cpumask(mm); > > > + struct cpumask *cmask, full_cmask; > > > unsigned long asid =3D FLUSH_TLB_NO_ASID; > > > - unsigned int cpuid; > > > bool broadcast; > > > > > > - if (cpumask_empty(cmask)) > > > - return; > > > + if (mm) { > > > + unsigned int cpuid; > > > + > > > + cmask =3D mm_cpumask(mm); > > > + if (cpumask_empty(cmask)) > > > + return; > > > > > > - cpuid =3D get_cpu(); > > > - /* check if the tlbflush needs to be sent to other CPUs */ > > > - broadcast =3D cpumask_any_but(cmask, cpuid) < nr_cpu_ids; > > > + cpuid =3D get_cpu(); > > > + /* check if the tlbflush needs to be sent to other CP= Us */ > > > + broadcast =3D cpumask_any_but(cmask, cpuid) < nr_cpu_= ids; > > > + } else { > > > + cpumask_setall(&full_cmask); > > > + cmask =3D &full_cmask; > > > + broadcast =3D true; > > > + } > > > > > > - if (static_branch_unlikely(&use_asid_allocator)) > > > + if (static_branch_unlikely(&use_asid_allocator) && mm) > > > asid =3D atomic_long_read(&mm->context.id) & asid_mas= k; > > > > > > if (broadcast) { > > > @@ -128,7 +136,8 @@ static void __flush_tlb_range(struct mm_struct *m= m, unsigned long start, > > > local_flush_tlb_range_asid(start, size, stride, asid)= ; > > > } > > > > > > - put_cpu(); > > > + if (mm) > > > + put_cpu(); > > > } > > > > > > void flush_tlb_mm(struct mm_struct *mm) > > > @@ -189,6 +198,12 @@ void flush_tlb_range(struct vm_area_struct *vma,= unsigned long start, > > > > > > __flush_tlb_range(vma->vm_mm, start, end - start, stride_size= ); > > > } > > > + > > > +void flush_tlb_kernel_range(unsigned long start, unsigned long end) > > > +{ > > > + __flush_tlb_range(NULL, start, end - start, PAGE_SIZE); > > > +} > > > + > > > #ifdef CONFIG_TRANSPARENT_HUGEPAGE > > > void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long s= tart, > > > unsigned long end) > > > -- > > > 2.39.2 > > >