From: Alexandre Ghiti <alexghiti@rivosinc.com>
To: Samuel Holland <samuel.holland@sifive.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-mm@kvack.org
Subject: Re: [PATCH v4 05/12] riscv: mm: Combine the SMP and UP TLB flush code
Date: Thu, 4 Jan 2024 13:36:37 +0100 [thread overview]
Message-ID: <CAHVXubi5C=Dt2ACsEYt68AeCSCVO49Udaks=0pf1+cK0igNOoQ@mail.gmail.com> (raw)
In-Reply-To: <20240102220134.3229156-6-samuel.holland@sifive.com>
On Tue, Jan 2, 2024 at 11:01 PM Samuel Holland
<samuel.holland@sifive.com> wrote:
>
> In SMP configurations, all TLB flushing narrower than flush_tlb_all()
> goes through __flush_tlb_range(). Do the same in UP configurations.
>
> This allows UP configurations to take advantage of recent improvements
> to the code in tlbflush.c, such as support for huge pages and flushing
> multiple-page ranges.
>
> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
> ---
>
> Changes in v4:
> - Merge the two copies of __flush_tlb_range() and rely on the compiler
> to optimize out the broadcast path (both clang and gcc do this)
> - Merge the two copies of flush_tlb_all() and rely on constant folding
>
> Changes in v2:
> - Move the SMP/UP merge earlier in the series to avoid build issues
> - Make a copy of __flush_tlb_range() instead of adding ifdefs inside
> - local_flush_tlb_all() is the only function used on !MMU (smpboot.c)
>
> arch/riscv/include/asm/tlbflush.h | 29 +++--------------------------
> arch/riscv/mm/Makefile | 5 +----
> 2 files changed, 4 insertions(+), 30 deletions(-)
>
> diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h
> index 8f3418c5f172..7712ffe2f6c4 100644
> --- a/arch/riscv/include/asm/tlbflush.h
> +++ b/arch/riscv/include/asm/tlbflush.h
> @@ -27,12 +27,7 @@ static inline void local_flush_tlb_page(unsigned long addr)
> {
> ALT_FLUSH_TLB_PAGE(__asm__ __volatile__ ("sfence.vma %0" : : "r" (addr) : "memory"));
> }
> -#else /* CONFIG_MMU */
> -#define local_flush_tlb_all() do { } while (0)
> -#define local_flush_tlb_page(addr) do { } while (0)
> -#endif /* CONFIG_MMU */
>
> -#if defined(CONFIG_SMP) && defined(CONFIG_MMU)
> void flush_tlb_all(void);
> void flush_tlb_mm(struct mm_struct *mm);
> void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
> @@ -46,26 +41,8 @@ void flush_tlb_kernel_range(unsigned long start, unsigned long end);
> void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start,
> unsigned long end);
> #endif
> -#else /* CONFIG_SMP && CONFIG_MMU */
> -
> -#define flush_tlb_all() local_flush_tlb_all()
> -#define flush_tlb_page(vma, addr) local_flush_tlb_page(addr)
> -
> -static inline void flush_tlb_range(struct vm_area_struct *vma,
> - unsigned long start, unsigned long end)
> -{
> - local_flush_tlb_all();
> -}
> -
> -/* Flush a range of kernel pages */
> -static inline void flush_tlb_kernel_range(unsigned long start,
> - unsigned long end)
> -{
> - local_flush_tlb_all();
> -}
> -
> -#define flush_tlb_mm(mm) flush_tlb_all()
> -#define flush_tlb_mm_range(mm, start, end, page_size) flush_tlb_all()
> -#endif /* !CONFIG_SMP || !CONFIG_MMU */
> +#else /* CONFIG_MMU */
> +#define local_flush_tlb_all() do { } while (0)
> +#endif /* CONFIG_MMU */
>
> #endif /* _ASM_RISCV_TLBFLUSH_H */
> diff --git a/arch/riscv/mm/Makefile b/arch/riscv/mm/Makefile
> index 3a4dfc8babcf..96e65c571ce8 100644
> --- a/arch/riscv/mm/Makefile
> +++ b/arch/riscv/mm/Makefile
> @@ -13,15 +13,12 @@ endif
> KCOV_INSTRUMENT_init.o := n
>
> obj-y += init.o
> -obj-$(CONFIG_MMU) += extable.o fault.o pageattr.o
> +obj-$(CONFIG_MMU) += extable.o fault.o pageattr.o tlbflush.o
> obj-y += cacheflush.o
> obj-y += context.o
> obj-y += pgtable.o
> obj-y += pmem.o
>
> -ifeq ($(CONFIG_MMU),y)
> -obj-$(CONFIG_SMP) += tlbflush.o
> -endif
> obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o
> obj-$(CONFIG_PTDUMP_CORE) += ptdump.o
> obj-$(CONFIG_KASAN) += kasan_init.o
> --
> 2.42.0
>
Nice one, you can add:
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Thanks,
Alex
next prev parent reply other threads:[~2024-01-04 12:36 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-02 22:00 [PATCH v4 00/12] riscv: ASID-related and UP-related TLB flush enhancements Samuel Holland
2024-01-02 22:00 ` [PATCH v4 01/12] riscv: Flush the instruction cache during SMP bringup Samuel Holland
2024-01-04 11:58 ` Alexandre Ghiti
2024-01-02 22:00 ` [PATCH v4 02/12] riscv: Use IPIs for remote cache/TLB flushes by default Samuel Holland
2024-01-04 12:09 ` Alexandre Ghiti
2024-01-02 22:00 ` [PATCH v4 03/12] riscv: mm: Broadcast kernel TLB flushes only when needed Samuel Holland
2024-01-04 12:15 ` Alexandre Ghiti
2024-01-02 22:00 ` [PATCH v4 04/12] riscv: Only send remote fences when some other CPU is online Samuel Holland
2024-01-03 14:57 ` Jisheng Zhang
2024-01-03 15:04 ` Jisheng Zhang
2024-01-04 12:33 ` Alexandre Ghiti
2024-01-04 15:33 ` Samuel Holland
2024-01-02 22:00 ` [PATCH v4 05/12] riscv: mm: Combine the SMP and UP TLB flush code Samuel Holland
2024-01-04 12:36 ` Alexandre Ghiti [this message]
2024-01-02 22:00 ` [PATCH v4 06/12] riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma Samuel Holland
2024-01-02 22:00 ` [PATCH v4 07/12] riscv: Avoid TLB flush loops when affected by SiFive CIP-1200 Samuel Holland
2024-01-02 22:00 ` [PATCH v4 08/12] riscv: mm: Introduce cntx2asid/cntx2version helper macros Samuel Holland
2024-01-04 12:39 ` Alexandre Ghiti
2024-01-04 15:42 ` Samuel Holland
2024-01-02 22:00 ` [PATCH v4 09/12] riscv: mm: Use a fixed layout for the MM context ID Samuel Holland
2024-01-04 12:42 ` Alexandre Ghiti
2024-01-02 22:00 ` [PATCH v4 10/12] riscv: mm: Make asid_bits a local variable Samuel Holland
2024-01-03 15:00 ` Jisheng Zhang
2024-01-04 15:49 ` Samuel Holland
2024-01-04 12:47 ` Alexandre Ghiti
2024-01-02 22:00 ` [PATCH v4 11/12] riscv: mm: Preserve global TLB entries when switching contexts Samuel Holland
2024-01-04 12:55 ` Alexandre Ghiti
2024-01-02 22:00 ` [PATCH v4 12/12] riscv: mm: Always use an ASID to flush mm contexts Samuel Holland
2024-01-03 15:02 ` Jisheng Zhang
2024-01-04 15:50 ` Samuel Holland
2024-01-04 13:01 ` Alexandre Ghiti
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