From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B92CC47074 for ; Thu, 4 Jan 2024 12:09:42 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id C04B36B036C; Thu, 4 Jan 2024 07:09:41 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id BDAD16B036D; Thu, 4 Jan 2024 07:09:41 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id AA36B6B036E; Thu, 4 Jan 2024 07:09:41 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0011.hostedemail.com [216.40.44.11]) by kanga.kvack.org (Postfix) with ESMTP id 9994C6B036C for ; Thu, 4 Jan 2024 07:09:41 -0500 (EST) Received: from smtpin22.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay02.hostedemail.com (Postfix) with ESMTP id 744AD1208EE for ; Thu, 4 Jan 2024 12:09:41 +0000 (UTC) X-FDA: 81641509362.22.5EFB32B Received: from mail-lf1-f54.google.com (mail-lf1-f54.google.com [209.85.167.54]) by imf02.hostedemail.com (Postfix) with ESMTP id 8F5B98001F for ; Thu, 4 Jan 2024 12:09:39 +0000 (UTC) Authentication-Results: imf02.hostedemail.com; dkim=pass header.d=rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=HT0RWD+K; spf=pass (imf02.hostedemail.com: domain of alexghiti@rivosinc.com designates 209.85.167.54 as permitted sender) smtp.mailfrom=alexghiti@rivosinc.com; dmarc=none ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1704370179; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=5OhX0VzJwMOMlPMl/O/UbwhUU6chhGIjYffCjj+4YjA=; b=faaVRYeDEZsFD8tdyIHBHfifNaF/NvGGVF1tWhmB9dn7yDPOI6k+eC1bCoGie06JQ7cl1y XVWOZODxwXRnho4W6aSyLzWJvBUqnWdLSoBbl6MzKCEtmOtpNoSb4oAP60NA8A5zTnzDdr JBHgtdpjkp/eG37L0ca5p0qEeD793iw= ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1704370179; a=rsa-sha256; cv=none; b=i80aTIXUd0lg3lXGgwYSaSN6hPItRv6VOO3X70ABEpJm2tw0I/vxhKCN5LWzNK+VyRXZ7t 60vOvv8+zCMWQ6WWvlyEtTOWjh0uPKbgEYgdBPZdPkDCz/HCi6xGONwRQMWXBM/aewNpRS 7ZUAuz47R7KRqrtBom8v/hTIWju/f2c= ARC-Authentication-Results: i=1; imf02.hostedemail.com; dkim=pass header.d=rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=HT0RWD+K; spf=pass (imf02.hostedemail.com: domain of alexghiti@rivosinc.com designates 209.85.167.54 as permitted sender) smtp.mailfrom=alexghiti@rivosinc.com; dmarc=none Received: by mail-lf1-f54.google.com with SMTP id 2adb3069b0e04-50e7f58c5fbso563207e87.1 for ; Thu, 04 Jan 2024 04:09:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1704370177; x=1704974977; darn=kvack.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=5OhX0VzJwMOMlPMl/O/UbwhUU6chhGIjYffCjj+4YjA=; b=HT0RWD+Kqel0juDms8VBO6M5w78U2U0fC+FOVUJkl8aa43NmLv1IgBQMHOeJIIDZ/g sul/d4UqFuJv8WT0FgDxRdDHSWdkRTvXl7RjoXg24vlNHpf8+0z0lRTF1yiEEDo6QMBs EyMVR+nx0Mc/3w4eblxXVMGxiB8Q/KAuWuWdv6ISo5HNo3F/fQ96IYz5CVZRWVmM+2cf uiXnC1xsIwqIgqY6HvmeW3iBN8L7bvDRvkp6q7I13eoHir8qAYx8W05EDhX50RdjEu8A 7bWZdZL09i0MP9yzsF/y1EqaWn9Isq2j9DKgkNmZ3Z/tPEz6P3GHNmNQ/6Um9Sbs/b85 s03A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704370177; x=1704974977; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5OhX0VzJwMOMlPMl/O/UbwhUU6chhGIjYffCjj+4YjA=; b=FhnIeZYtON53BHCIflK4uEOQ2El9L1SASuG31gEPDyUQmohAvadtX20i9ajb7CghpO LqEbzhzZUAiQZh/MiUrLsLqLiszqRWatBmHbvE9Z7hrqT0sSezx/BpVNDWxWMIZKl+Bm VKJHCbMvXUneF6TFeOHCsS9UMqoqkisbCcxVBbdAqlhRoPlX87L8mgAZiuUnzAVHXQBP /1fRgh78GasKnsLCla2Vnkw5oY/9aZqphkh8RSSZeqUvCUfJZZ3zQDAQ/95w8GfM+GVF lnRtYYuReMCMjeYm5DvflTDljLF73AgbhWltJZOiO1D/LUzAxG5Zxw7QdcOVpaEZX9gd Bv3g== X-Gm-Message-State: AOJu0YwPcPH89C/26oQOVQQvMYYjuQCmEAhMUKbGKqef3aVDEJD305kN sjpK6jpwGTkiWwzipGElDgPLmQ9PxdzQQIUjRqhK153/RKsCXw== X-Google-Smtp-Source: AGHT+IHz1HGtquuKHpa5k8LMx0cAtC2KImJu4U9ZaKRwSALvhrpqyubqXuJVZxO/KTRsfiL7ggCWifvCyA2mr0Ojx6Y= X-Received: by 2002:a05:6512:398f:b0:50e:a8c7:b2df with SMTP id j15-20020a056512398f00b0050ea8c7b2dfmr376322lfu.36.1704370177506; Thu, 04 Jan 2024 04:09:37 -0800 (PST) MIME-Version: 1.0 References: <20240102220134.3229156-1-samuel.holland@sifive.com> <20240102220134.3229156-3-samuel.holland@sifive.com> In-Reply-To: <20240102220134.3229156-3-samuel.holland@sifive.com> From: Alexandre Ghiti Date: Thu, 4 Jan 2024 13:09:26 +0100 Message-ID: Subject: Re: [PATCH v4 02/12] riscv: Use IPIs for remote cache/TLB flushes by default To: Samuel Holland Cc: Palmer Dabbelt , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Rspamd-Queue-Id: 8F5B98001F X-Rspam-User: X-Stat-Signature: j4mhnqz89ha99mpsr6ko5cfdu1mg9eqs X-Rspamd-Server: rspam03 X-HE-Tag: 1704370179-484675 X-HE-Meta: U2FsdGVkX18Bbfk3wdct3QyuqlwgH49z4kJnWzXCGrIsZ24fZfcq1pud2dorpqIgNPQsEtHjWL9aPCXzycMFrhzwQ9k42fwnny39/snziywGSBu/fH8C4NmK6ZqyH/1FAluMvB84V2Rq2Y2nxROmrZux8nhh79yfT7PlLjuPSC1WUjfq1+azx83EIRXW7WqaBBDxrG2Gjbow8tkGJCI6swr+HJ8Ta8nqhDyiQ3AO7NGPz0KMvtVfPW5mN7Cmyi4zF1XanB58OaVcwY+9UGlpUEnv3PgaIkEt8XCszSPWhPX4VJkUFihTeVFjLBNsk0gT/j4SjS2vJkCco0FN1OJqyI5vxmy24u4tbUlP0UfKlyNdZygLLJ3JGKmOqmXMjjuLrlcLn+WRzlbb3i/r1BMsVXas7GJhecvwpAy/gqB7QdyX9H8cj5NRpS2boPsJfV/wvn0B9t9EpzUJKVj94/gnVdSFJJX2bVofPNY/TbAIp9h69HmrQRw3m85r2HD+78CtUDfVNm+S6gIxASJzzCtTkKFRuMazy8J0WBmygbfiE87Z5tJu7EN8dSdk2txbe8iEJDfL5UBHWOVYoajazKRWBCZg9b0IZmmKvTFZV5BntHcRelxdvkSaINWhncDv0KxqlB9AurEXmEMxcny1tKAMFFL+bbv8OSO7Sn3n7kJcdt5R7EDNCm/jYg78eal35gtnKSy4wdNSqe9whbt7QdZQN5JyhFDccbCdMPwkjoeb7cOqdRlExOzPmajxKuvDe5/quuaziUL0aVFlUQb0Q/+JPj6nHO/K1YC2CW8r0FwvbNOrCd/M/tcX6ABqHZTrY4sZJVMKtEpeKpMl8vvvjolWqkFa140Jxz21Pl9L+uXG9d980ZhfQNGJlx9TQBtwUtHlPwZ+cBvUWjIjIVvTrJ2tfexaYej9zovyqMSi9cp8o5I/tYwA9VcN3nDeBXUEJudfKxkVez9p0MReWDyySPT CdjpfxeF dP4YVBQn//zzxPz483DHBUBvm0STsgm+O4gHi8RV8ByH8FvcLdcCwq30h2nu2lKM4iiXOG6iT+XpzYuMwbGvYn0R7f/9ftt6rSPOQqtBeB6wRVQXjGHnC24o9tYXBSqI1hSRDUpA4uKJBvefIQJfaM6RA+TN8tYcJ+exx/xFVqeBa9bq5IxnAARXWeE7WKGtFd5rhuLsZuIQmuvYbW1ixNqgh9+dUldYXrinBkNUhimnfjOuWeGWkW5tsKTtfdM3RAHHe7oJuMTnH0lMlMo7SsFqXRwz49uFhHCu11yz4o7YgwUekKKV+/XuDNUNQiJ1R8sIYk79p0rvqPxGFS08FNGThsIrQ4JBPOyK7tEqTuX5tKlnGMQzMeBrffplkrjyEQj99ip1MuE57dhOb8bim+R17KQyCFrnaUWuiIoXWzlX5qULz8Pcf06o04w== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: On Tue, Jan 2, 2024 at 11:01=E2=80=AFPM Samuel Holland wrote: > > An IPI backend is always required in an SMP configuration, but an SBI > implementation is not. For example, SBI will be unavailable when the > kernel runs in M mode. > > Generally, IPIs are assumed to be faster than SBI calls due to the SBI > context switch overhead. However, when SBI is used as the IPI backend, > then the context switch cost must be paid anyway, and performing the > cache/TLB flush directly in the SBI implementation is more efficient > than inserting an interrupt to the kernel. This is the only scenario > where riscv_ipi_set_virq_range()'s use_for_rfence parameter is false. > > Thus, it makes sense for remote fences to use IPIs by default, and make > the SBI remote fence extension the special case. > > sbi_ipi_init() already checks riscv_ipi_have_virq_range(), so it only > calls riscv_ipi_set_virq_range() when no other IPI device is available. > So we can move the static key and drop the use_for_rfence parameter. > > Furthermore, the static branch only makes sense when CONFIG_RISCV_SBI is > enabled. Optherwise, IPIs must be used. Add a fallback definition of > riscv_use_sbi_for_rfence() which handles this case and removes the need > to check CONFIG_RISCV_SBI elsewhere, such as in cacheflush.c. > > Signed-off-by: Samuel Holland > --- > > Changes in v4: > - New patch for v4 > > arch/riscv/include/asm/sbi.h | 4 ++++ > arch/riscv/include/asm/smp.h | 15 ++------------- > arch/riscv/kernel/sbi-ipi.c | 11 ++++++++++- > arch/riscv/kernel/smp.c | 11 +---------- > arch/riscv/mm/cacheflush.c | 5 ++--- > arch/riscv/mm/tlbflush.c | 31 ++++++++++++++----------------- > drivers/clocksource/timer-clint.c | 2 +- > 7 files changed, 34 insertions(+), 45 deletions(-) > > diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h > index 0892f4421bc4..aeee0127df76 100644 > --- a/arch/riscv/include/asm/sbi.h > +++ b/arch/riscv/include/asm/sbi.h > @@ -339,8 +339,12 @@ unsigned long riscv_cached_marchid(unsigned int cpu_= id); > unsigned long riscv_cached_mimpid(unsigned int cpu_id); > > #if IS_ENABLED(CONFIG_SMP) && IS_ENABLED(CONFIG_RISCV_SBI) > +DECLARE_STATIC_KEY_FALSE(riscv_sbi_for_rfence); > +#define riscv_use_sbi_for_rfence() \ > + static_branch_unlikely(&riscv_sbi_for_rfence) > void sbi_ipi_init(void); > #else > +static inline bool riscv_use_sbi_for_rfence(void) { return false; } > static inline void sbi_ipi_init(void) { } > #endif > > diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h > index 0d555847cde6..7ac80e9f2288 100644 > --- a/arch/riscv/include/asm/smp.h > +++ b/arch/riscv/include/asm/smp.h > @@ -49,12 +49,7 @@ void riscv_ipi_disable(void); > bool riscv_ipi_have_virq_range(void); > > /* Set the IPI interrupt numbers for arch (called by irqchip drivers) */ > -void riscv_ipi_set_virq_range(int virq, int nr, bool use_for_rfence); > - > -/* Check if we can use IPIs for remote FENCEs */ > -DECLARE_STATIC_KEY_FALSE(riscv_ipi_for_rfence); > -#define riscv_use_ipi_for_rfence() \ > - static_branch_unlikely(&riscv_ipi_for_rfence) > +void riscv_ipi_set_virq_range(int virq, int nr); > > /* Check other CPUs stop or not */ > bool smp_crash_stop_failed(void); > @@ -104,16 +99,10 @@ static inline bool riscv_ipi_have_virq_range(void) > return false; > } > > -static inline void riscv_ipi_set_virq_range(int virq, int nr, > - bool use_for_rfence) > +static inline void riscv_ipi_set_virq_range(int virq, int nr) > { > } > > -static inline bool riscv_use_ipi_for_rfence(void) > -{ > - return false; > -} > - > #endif /* CONFIG_SMP */ > > #if defined(CONFIG_HOTPLUG_CPU) && (CONFIG_SMP) > diff --git a/arch/riscv/kernel/sbi-ipi.c b/arch/riscv/kernel/sbi-ipi.c > index a4559695ce62..1026e22955cc 100644 > --- a/arch/riscv/kernel/sbi-ipi.c > +++ b/arch/riscv/kernel/sbi-ipi.c > @@ -13,6 +13,9 @@ > #include > #include > > +DEFINE_STATIC_KEY_FALSE(riscv_sbi_for_rfence); > +EXPORT_SYMBOL_GPL(riscv_sbi_for_rfence); > + > static int sbi_ipi_virq; > > static void sbi_ipi_handle(struct irq_desc *desc) > @@ -72,6 +75,12 @@ void __init sbi_ipi_init(void) > "irqchip/sbi-ipi:starting", > sbi_ipi_starting_cpu, NULL); > > - riscv_ipi_set_virq_range(virq, BITS_PER_BYTE, false); > + riscv_ipi_set_virq_range(virq, BITS_PER_BYTE); > pr_info("providing IPIs using SBI IPI extension\n"); > + > + /* > + * Use the SBI remote fence extension to avoid > + * the extra context switch needed to handle IPIs. > + */ > + static_branch_enable(&riscv_sbi_for_rfence); > } > diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c > index 40420afbb1a0..1d06df04eb71 100644 > --- a/arch/riscv/kernel/smp.c > +++ b/arch/riscv/kernel/smp.c > @@ -171,10 +171,7 @@ bool riscv_ipi_have_virq_range(void) > return (ipi_virq_base) ? true : false; > } > > -DEFINE_STATIC_KEY_FALSE(riscv_ipi_for_rfence); > -EXPORT_SYMBOL_GPL(riscv_ipi_for_rfence); > - > -void riscv_ipi_set_virq_range(int virq, int nr, bool use_for_rfence) > +void riscv_ipi_set_virq_range(int virq, int nr) > { > int i, err; > > @@ -197,12 +194,6 @@ void riscv_ipi_set_virq_range(int virq, int nr, bool= use_for_rfence) > > /* Enabled IPIs for boot CPU immediately */ > riscv_ipi_enable(); > - > - /* Update RFENCE static key */ > - if (use_for_rfence) > - static_branch_enable(&riscv_ipi_for_rfence); > - else > - static_branch_disable(&riscv_ipi_for_rfence); > } > > static const char * const ipi_names[] =3D { > diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c > index 55a34f2020a8..47c485bc7df0 100644 > --- a/arch/riscv/mm/cacheflush.c > +++ b/arch/riscv/mm/cacheflush.c > @@ -21,7 +21,7 @@ void flush_icache_all(void) > { > local_flush_icache_all(); > > - if (IS_ENABLED(CONFIG_RISCV_SBI) && !riscv_use_ipi_for_rfence()) > + if (riscv_use_sbi_for_rfence()) > sbi_remote_fence_i(NULL); > else > on_each_cpu(ipi_remote_fence_i, NULL, 1); > @@ -69,8 +69,7 @@ void flush_icache_mm(struct mm_struct *mm, bool local) > * with flush_icache_deferred(). > */ > smp_mb(); > - } else if (IS_ENABLED(CONFIG_RISCV_SBI) && > - !riscv_use_ipi_for_rfence()) { > + } else if (riscv_use_sbi_for_rfence()) { > sbi_remote_fence_i(&others); > } else { > on_each_cpu_mask(&others, ipi_remote_fence_i, NULL, 1); > diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c > index e6659d7368b3..09b03bf71e6a 100644 > --- a/arch/riscv/mm/tlbflush.c > +++ b/arch/riscv/mm/tlbflush.c > @@ -73,10 +73,10 @@ static void __ipi_flush_tlb_all(void *info) > > void flush_tlb_all(void) > { > - if (riscv_use_ipi_for_rfence()) > - on_each_cpu(__ipi_flush_tlb_all, NULL, 1); > - else > + if (riscv_use_sbi_for_rfence()) > sbi_remote_sfence_vma_asid(NULL, 0, FLUSH_TLB_MAX_SIZE, F= LUSH_TLB_NO_ASID); > + else > + on_each_cpu(__ipi_flush_tlb_all, NULL, 1); > } > > struct flush_tlb_range_data { > @@ -96,7 +96,6 @@ static void __ipi_flush_tlb_range_asid(void *info) > static void __flush_tlb_range(struct mm_struct *mm, unsigned long start, > unsigned long size, unsigned long stride) > { > - struct flush_tlb_range_data ftd; > const struct cpumask *cmask; > unsigned long asid =3D FLUSH_TLB_NO_ASID; > bool broadcast; > @@ -119,20 +118,18 @@ static void __flush_tlb_range(struct mm_struct *mm,= unsigned long start, > broadcast =3D true; > } > > - if (broadcast) { > - if (riscv_use_ipi_for_rfence()) { > - ftd.asid =3D asid; > - ftd.start =3D start; > - ftd.size =3D size; > - ftd.stride =3D stride; > - on_each_cpu_mask(cmask, > - __ipi_flush_tlb_range_asid, > - &ftd, 1); > - } else > - sbi_remote_sfence_vma_asid(cmask, > - start, size, asid); > - } else { > + if (!broadcast) { > local_flush_tlb_range_asid(start, size, stride, asid); > + } else if (riscv_use_sbi_for_rfence()) { > + sbi_remote_sfence_vma_asid(cmask, start, size, asid); > + } else { > + struct flush_tlb_range_data ftd; > + > + ftd.asid =3D asid; > + ftd.start =3D start; > + ftd.size =3D size; > + ftd.stride =3D stride; > + on_each_cpu_mask(cmask, __ipi_flush_tlb_range_asid, &ftd,= 1); > } > > if (mm) > diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/time= r-clint.c > index 9a55e733ae99..7ccc16dd6a76 100644 > --- a/drivers/clocksource/timer-clint.c > +++ b/drivers/clocksource/timer-clint.c > @@ -251,7 +251,7 @@ static int __init clint_timer_init_dt(struct device_n= ode *np) > } > > irq_set_chained_handler(clint_ipi_irq, clint_ipi_interrupt); > - riscv_ipi_set_virq_range(rc, BITS_PER_BYTE, true); > + riscv_ipi_set_virq_range(rc, BITS_PER_BYTE); > clint_clear_ipi(); > #endif > > -- > 2.42.0 > You can add: Reviewed-by: Alexandre Ghiti Thanks, Alex