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Thu, 04 Jan 2024 04:43:06 -0800 (PST) MIME-Version: 1.0 References: <20240102220134.3229156-1-samuel.holland@sifive.com> <20240102220134.3229156-10-samuel.holland@sifive.com> In-Reply-To: <20240102220134.3229156-10-samuel.holland@sifive.com> From: Alexandre Ghiti Date: Thu, 4 Jan 2024 13:42:55 +0100 Message-ID: Subject: Re: [PATCH v4 09/12] riscv: mm: Use a fixed layout for the MM context ID To: Samuel Holland Cc: Palmer Dabbelt , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Rspamd-Queue-Id: CB41CC0004 X-Rspam-User: X-Stat-Signature: 11tmenrhapea1afqbikhqfr6f8ctngcq X-Rspamd-Server: rspam01 X-HE-Tag: 1704372187-451185 X-HE-Meta: U2FsdGVkX19Tstb0fsFmucAqp/J4H2W85AXKJ3mOXJG1KzWHe4tn5Z4oWk/8+h2j2UYp4f28PbllpI4dCKynDsIKxr0uPIG7NUtDV8ar8SPWtvUAIN7FwuV8NeZhGdjyz3BS5xws2RnJgp60VrpDFwLw2wNvMCYVal3YkwkzJgZ4zzpkU9cO5qS4zRy1TjGiKPFUsPLsb3LCO6FvwnDJwoGI6HjhDd0HTv+S63ZytMpsmALr4cBNQSSUb5PAwhzLEUbv3DGqbcIH14Tz0lcaTp4VV1HtLkC/kn8ZOMsUaCo7HIdEJ8UwBogOdIrgaHX56KRK07EtktMWhYDsxVWgDB4mv6FFBjZdNuiPhnP91uiXscnRWHZ+/E2LeiaA7Ep6TDSNDCY8ZjnSmcUnfhuA1HBuhcVoG75RJz53yvE4lNbCq/Cbak0Sp6PpZ08u563cSIjtcPOW53NX5I/pRc2HyPrIdecUa/cjzOYVUB2VXfftXL89HfnJtHX62BcBBSAbD1NX4NDfyvyaN2LoHsKJB0CINK4XuxdrOR05EGVN9wntQlMA1DjTMX6tZonQufdrQo0wTIO9GzAXcjUKhd5+MTqCPFlwRZX3ZAuAK5hEOXCOPS2FganjedsA5OL0VknLN3vkFJA7xahX2kLYD7d/Az2YBTVze2xuBJ/X1NLSAAjxsuQjRuxOXg6eLv6YTIyQ91iCAhYFMrj1iYU8E/WZaZ4D800A/CT4pvO6LO8tkExCsikDUo4cPT3lKlBgjdfLLZvpr3SR2+eTyJA7wKNL0piOamK3/HsffLS5m2cxdE6dLbV2UxnyLb1dUDyBzA+yb1L82vsRGvTZQmr4LNMTBWdbbsM1MgAQS5UTCzdU+ORscxUbyp1f6lE42kXdnB9DLDXrfC9EkRUO1x64H6vCrR36cu1nHBm4JJryoQj/EYuV0gAWs51SyRrGq6QHQkhDNVyLlcM4D6sDbV/htHg LQVzW2WW /1Nc1bx/LvuK7SDQ14TpbpU3wXhoMHlWqgpOq X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: On Tue, Jan 2, 2024 at 11:01=E2=80=AFPM Samuel Holland wrote: > > Currently, the size of the ASID field in the MM context ID dynamically > depends on the number of hardware-supported ASID bits. This requires > reading a global variable to extract either field from the context ID. > Instead, allocate the maximum possible number of bits to the ASID field, > so the layout of the context ID is known at compile-time. > > Signed-off-by: Samuel Holland > --- > > (no changes since v1) > > arch/riscv/include/asm/mmu.h | 4 ++-- > arch/riscv/include/asm/tlbflush.h | 2 -- > arch/riscv/mm/context.c | 6 ++---- > 3 files changed, 4 insertions(+), 8 deletions(-) > > diff --git a/arch/riscv/include/asm/mmu.h b/arch/riscv/include/asm/mmu.h > index a550fbf770be..dc0273f7905f 100644 > --- a/arch/riscv/include/asm/mmu.h > +++ b/arch/riscv/include/asm/mmu.h > @@ -26,8 +26,8 @@ typedef struct { > #endif > } mm_context_t; > > -#define cntx2asid(cntx) ((cntx) & asid_mask) > -#define cntx2version(cntx) ((cntx) & ~asid_mask) > +#define cntx2asid(cntx) ((cntx) & SATP_ASID_MASK) > +#define cntx2version(cntx) ((cntx) & ~SATP_ASID_MASK) > > void __init create_pgd_mapping(pgd_t *pgdp, uintptr_t va, phys_addr_t pa= , > phys_addr_t sz, pgprot_t prot); > diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/t= lbflush.h > index d9913590f82e..5bfd37cfd8c3 100644 > --- a/arch/riscv/include/asm/tlbflush.h > +++ b/arch/riscv/include/asm/tlbflush.h > @@ -15,8 +15,6 @@ > #define FLUSH_TLB_NO_ASID ((unsigned long)-1) > > #ifdef CONFIG_MMU > -extern unsigned long asid_mask; > - > static inline void local_flush_tlb_all(void) > { > __asm__ __volatile__ ("sfence.vma" : : : "memory"); > diff --git a/arch/riscv/mm/context.c b/arch/riscv/mm/context.c > index 43d005f63253..b5170ac1b742 100644 > --- a/arch/riscv/mm/context.c > +++ b/arch/riscv/mm/context.c > @@ -22,7 +22,6 @@ DEFINE_STATIC_KEY_FALSE(use_asid_allocator); > > static unsigned long asid_bits; > static unsigned long num_asids; > -unsigned long asid_mask; > > static atomic_long_t current_version; > > @@ -128,7 +127,7 @@ static unsigned long __new_context(struct mm_struct *= mm) > goto set_asid; > > /* We're out of ASIDs, so increment current_version */ > - ver =3D atomic_long_add_return_relaxed(num_asids, ¤t_versio= n); > + ver =3D atomic_long_add_return_relaxed(BIT(SATP_ASID_BITS), &curr= ent_version); > > /* Flush everything */ > __flush_context(); > @@ -247,7 +246,6 @@ static int __init asids_init(void) > /* Pre-compute ASID details */ > if (asid_bits) { > num_asids =3D 1 << asid_bits; > - asid_mask =3D num_asids - 1; > } > > /* > @@ -255,7 +253,7 @@ static int __init asids_init(void) > * at-least twice more than CPUs > */ > if (num_asids > (2 * num_possible_cpus())) { > - atomic_long_set(¤t_version, num_asids); > + atomic_long_set(¤t_version, BIT(SATP_ASID_BITS)); > > context_asid_map =3D bitmap_zalloc(num_asids, GFP_KERNEL)= ; > if (!context_asid_map) > -- > 2.42.0 > You can add: Reviewed-by: Alexandre Ghiti Thanks, Alex