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AJvYcCWPL7L6M/yR+YQQ9mrD2FvsI3PmauWIVONfGZ1ylaA0Gmye4EQLj4sVP6Zs3Q/HnT8iuFiUbejcIQ==@kvack.org X-Gm-Message-State: AOJu0YyXoN99LIpZmdyZmYAhvEOWZsD9zxBNR8nf6E8NkfGhXc1hMKr/ 9mJzDB667VrXG9b9jb1LAprgyb//rnNlPxgUPP4rLuPJ2i+7rp0p3UvwWnPImEm7jb4niMrWBTg 5d00C8Nv2oO/BkbOqtdRmh03GAVU= X-Gm-Gg: ASbGncviZCJ+Bgwn2WxWtKhattnRzkagY1YGoHTkjVQ3zPrvLWydEbfb2oBYljqmwGc ZBx41fzamlrCBo4NwR2P8Qws+MqozmLjogCUDhwRP/30bcP8BGuypq8HSyrRU9zn8N77at2ic X-Google-Smtp-Source: AGHT+IHI2AkOM8Hk95tvTRn7haGosukJN9wvnMrwUWz32Bwljqr7HCbWbJWPleVqx7F/PaKwYeTCyUr8eVtGz6JR8qY= X-Received: by 2002:a05:6102:3ca0:b0:4b2:5c4b:5186 with SMTP id ada2fe7eead31-4b3d0fe692emr21832774137.23.1736851069161; Tue, 14 Jan 2025 02:37:49 -0800 (PST) MIME-Version: 1.0 References: <20250113033901.68951-1-21cnbao@gmail.com> <20250113033901.68951-3-21cnbao@gmail.com> In-Reply-To: From: Barry Song <21cnbao@gmail.com> Date: Tue, 14 Jan 2025 23:37:38 +1300 X-Gm-Features: AbW1kvb9zzKL_PAv-K0B9SXy-8Bp_Lg8h_lTkXYhRj7eUJYcRuyixwa4RAHqIWw Message-ID: Subject: Re: [PATCH v2 2/4] mm: Support tlbbatch flush for a range of PTEs To: David Hildenbrand Cc: akpm@linux-foundation.org, linux-mm@kvack.org, baolin.wang@linux.alibaba.com, chrisl@kernel.org, ioworker0@gmail.com, kasong@tencent.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, ryan.roberts@arm.com, v-songbaohua@oppo.com, x86@kernel.org, linux-riscv@lists.infradead.org, ying.huang@intel.com, zhengtangquan@oppo.com, lorenzo.stoakes@oracle.com, Catalin Marinas , Will Deacon , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Anshuman Khandual , Shaoqin Huang , Gavin Shan , Kefeng Wang , Mark Rutland , "Kirill A. Shutemov" , Yosry Ahmed , Paul Walmsley , Palmer Dabbelt , Albert Ou , Yicong Yang Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Stat-Signature: auox8medpcs1adppz54kspjxfoxonitz X-Rspamd-Queue-Id: 29573180010 X-Rspam-User: X-Rspamd-Server: rspam01 X-HE-Tag: 1736851069-758487 X-HE-Meta: U2FsdGVkX1/yiBKPmGaJjGJq+9A2D/FWbRJWPZergkBh4eh0J5SVE0cm4ymVK0bq19RiJ6Q2r8H5hUcPNjbkX6AQlKVg1yVvIiQXWdvmOoO8hmFXZtTc8y8uZBw0bgKGvzOUmBKaYiRA/Al6sRpWvVHV0RAv0H7xtX40tMngWH0jxBGvCyTwXgmo1vhQPrMbZutRChjqhWMUaBA07l0R8m/CnrXh5Z3VM63q/Z+OyoH0mUh4CH0fexVpbt1a14pZ8hecm73ErjqCbd2cJXpAzMV64QAScE84fbkgNSEqGa5EYp0jT1vpTJ6Wlrmfv3QHZPzENPhL5OSxapxSvizeyM0y9qnb7yZkxEXmE7RJHYf3uAej0w7Gos8HwfcSFZIpoCA0lgZZl746Hp3O1/Bkw7Nl13B9qeHfrVy6LHxum+2A9/e5x3ACqe4svB7EldkX7uPkU/iUsgg9nJofXUmizeSsgYzavV+2Q14MHG2XxG5zrrF294SMcv7NcXqi4P0WRe7L8ozycBmB+JHlW3wDoFIo9lBrfciK2VWTjHTqoO7/yhP4JWMR/o3WthV0V87V3PTqUZ3io0fYrXNmQbfbE+bDafIqgLtHdgVzQeKy0iSti6KrSHVoXpuJvgFuWs21ZgNKqpnACK2tz+72yvU6Oh1REfjq0ZiVvOjTFHEbbsFN8f1plbnGoIRzP94m0DIgYNLFX3Kwe4bqpFf1v9RQsuiKAS1etm8fGxv3qmQVAh8PmT2juHwTa9ZNxmZ1p5gbgjSW3posgeDbvczrZNc6vlNr+XdMGqC8ftecBSbByeSPHNOSJrfFDL5EJ7Z57EpugANzfiJ1s2ajOCNXu4V6UpU9pq5Uz8DiXhk7f2PWN1FubRsmfz54tbXOL6zb2mGAUHlMkVZgCnJqIORBM39vAZ4MewF/CD0EkoC7rKdWMjB2q1P7GaZOlrfVf/TAjdtxQqLZJM9DznLW2xmjpaT gjm1h/iP o1URKIrtqDsnTBx0nQG0L0yZZGXnPLUWBJX3h7LM3tOZ3JOm98uWirto7bAQge0ESeRoVF1WSySIbV7TDxPP5FarU8Mce8jRa38DNo+LLlMoisRxVdslO3azPCP2Nukqr4aByDRiNmHaPPzXk19t910XjQ48nPk+7+2iChoHkFHfIaILVA/0MoYYoy0ylfKsUjeT0W5Ozk9tePK3ylpKPFOZ+dCnNBC/4Z2bxbN4RSSzbkiSrFx6UBlYNMNuIcaQ/jMBILhYqid3+s+7siTJzPLuus0PmCeF0qvViSOuoe2dgZYhpWnAQISYp4xyiTJryaRLDo79nqKuL+nMtT4e0OU73Yzux7T3SXdfwgzZeYqp70/x4f1PIsmBIrTKfybeyiwGBqB8iq0wRuhc7BzHsa8BuwULLJosPU7YfjTI+a6x1YxElQrDq71iJpxH/MxCImF15iKXwZiunn//+c0goRrYtA7ywWM8HWpqB4BYeKmpOcQwpBd3kTVx9D3mN05VCi17F//Byz5evD0RrzXgas+L/S+f8In2t/shEfpgNKG3+3Nq6/mRLEv9pq47Eaikl9pgAvkkONzfyL/EDuS+QtteYYlmvDKO8IkJOqRAjrzU2hOqiejiYvR86lBAbzHkOybGTA8tFV7vITMOXe+URaCv9bp6r9+zp7o98jx4EHyXddEgx+M7tjAStIGGH4LLMT58+gawtbcUuY7WZWJh0P7mBIyVvdgvQ0DGpQmpWq2ycExqXNUYl+tq/8XkYWpJRn34hjMRlqCc+lFdoX2oLBWgItw== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: On Tue, Jan 14, 2025 at 10:52=E2=80=AFPM David Hildenbrand wrote: > > On 13.01.25 04:38, Barry Song wrote: > > From: Barry Song > > > > This is a preparatory patch to support batch PTE unmapping in > > `try_to_unmap_one`. It first introduces range handling for > > `tlbbatch` flush. Currently, the range is always set to the size of > > PAGE_SIZE. > > You could have spelled out why you perform the VMA -> MM change. Sure, I=E2=80=99ll include some additional details in v3. > > > > > Cc: Catalin Marinas > > Cc: Will Deacon > > Cc: Thomas Gleixner > > Cc: Ingo Molnar > > Cc: Borislav Petkov > > Cc: Dave Hansen > > Cc: "H. Peter Anvin" > > Cc: Anshuman Khandual > > Cc: Ryan Roberts > > Cc: Shaoqin Huang > > Cc: Gavin Shan > > Cc: Kefeng Wang > > Cc: Mark Rutland > > Cc: David Hildenbrand > > Cc: Lance Yang > > Cc: "Kirill A. Shutemov" > > Cc: Yosry Ahmed > > Cc: Paul Walmsley > > Cc: Palmer Dabbelt > > Cc: Albert Ou > > Cc: Yicong Yang > > Signed-off-by: Barry Song > > --- > > arch/arm64/include/asm/tlbflush.h | 26 ++++++++++++++------------ > > arch/arm64/mm/contpte.c | 2 +- > > arch/riscv/include/asm/tlbflush.h | 3 ++- > > arch/riscv/mm/tlbflush.c | 3 ++- > > arch/x86/include/asm/tlbflush.h | 3 ++- > > mm/rmap.c | 12 +++++++----- > > 6 files changed, 28 insertions(+), 21 deletions(-) > > > > diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm= /tlbflush.h > > index bc94e036a26b..f34e4fab5aa2 100644 > > --- a/arch/arm64/include/asm/tlbflush.h > > +++ b/arch/arm64/include/asm/tlbflush.h > > @@ -322,13 +322,6 @@ static inline bool arch_tlbbatch_should_defer(stru= ct mm_struct *mm) > > return true; > > } > > > > -static inline void arch_tlbbatch_add_pending(struct arch_tlbflush_unma= p_batch *batch, > > - struct mm_struct *mm, > > - unsigned long uaddr) > > -{ > > - __flush_tlb_page_nosync(mm, uaddr); > > -} > > - > > /* > > * If mprotect/munmap/etc occurs during TLB batched flushing, we need= to > > * synchronise all the TLBI issued with a DSB to avoid the race menti= oned in > > @@ -448,7 +441,7 @@ static inline bool __flush_tlb_range_limit_excess(u= nsigned long start, > > return false; > > } > > > > -static inline void __flush_tlb_range_nosync(struct vm_area_struct *vma= , > > +static inline void __flush_tlb_range_nosync(struct mm_struct *mm, > > unsigned long start, unsigned long e= nd, > > unsigned long stride, bool last_leve= l, > > int tlb_level) > > @@ -460,12 +453,12 @@ static inline void __flush_tlb_range_nosync(struc= t vm_area_struct *vma, > > pages =3D (end - start) >> PAGE_SHIFT; > > > > if (__flush_tlb_range_limit_excess(start, end, pages, stride)) { > > - flush_tlb_mm(vma->vm_mm); > > + flush_tlb_mm(mm); > > return; > > } > > > > dsb(ishst); > > - asid =3D ASID(vma->vm_mm); > > + asid =3D ASID(mm); > > > > if (last_level) > > __flush_tlb_range_op(vale1is, start, pages, stride, asid, > > @@ -474,7 +467,7 @@ static inline void __flush_tlb_range_nosync(struct = vm_area_struct *vma, > > __flush_tlb_range_op(vae1is, start, pages, stride, asid, > > tlb_level, true, lpa2_is_enabled()); > > > > - mmu_notifier_arch_invalidate_secondary_tlbs(vma->vm_mm, start, en= d); > > + mmu_notifier_arch_invalidate_secondary_tlbs(mm, start, end); > > } > > > > static inline void __flush_tlb_range(struct vm_area_struct *vma, > > @@ -482,7 +475,7 @@ static inline void __flush_tlb_range(struct vm_area= _struct *vma, > > unsigned long stride, bool last_leve= l, > > int tlb_level) > > { > > - __flush_tlb_range_nosync(vma, start, end, stride, > > + __flush_tlb_range_nosync(vma->vm_mm, start, end, stride, > > last_level, tlb_level); > > dsb(ish); > > } > > @@ -533,6 +526,15 @@ static inline void __flush_tlb_kernel_pgtable(unsi= gned long kaddr) > > dsb(ish); > > isb(); > > } > > + > > +static inline void arch_tlbbatch_add_pending(struct arch_tlbflush_unma= p_batch *batch, > > + struct mm_struct *mm, > > + unsigned long uaddr, > > + unsigned long size) > > +{ > > + __flush_tlb_range_nosync(mm, uaddr, uaddr + size, > > + PAGE_SIZE, true, 3); > > +} > > #endif > > > > #endif > > diff --git a/arch/arm64/mm/contpte.c b/arch/arm64/mm/contpte.c > > index 55107d27d3f8..bcac4f55f9c1 100644 > > --- a/arch/arm64/mm/contpte.c > > +++ b/arch/arm64/mm/contpte.c > > @@ -335,7 +335,7 @@ int contpte_ptep_clear_flush_young(struct vm_area_s= truct *vma, > > * eliding the trailing DSB applies here. > > */ > > addr =3D ALIGN_DOWN(addr, CONT_PTE_SIZE); > > - __flush_tlb_range_nosync(vma, addr, addr + CONT_PTE_SIZE, > > + __flush_tlb_range_nosync(vma->vm_mm, addr, addr + CONT_PT= E_SIZE, > > PAGE_SIZE, true, 3); > > } > > > > diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm= /tlbflush.h > > index 72e559934952..7f3ea687ce33 100644 > > --- a/arch/riscv/include/asm/tlbflush.h > > +++ b/arch/riscv/include/asm/tlbflush.h > > @@ -61,7 +61,8 @@ void flush_pmd_tlb_range(struct vm_area_struct *vma, = unsigned long start, > > bool arch_tlbbatch_should_defer(struct mm_struct *mm); > > void arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_batch *batc= h, > > struct mm_struct *mm, > > - unsigned long uaddr); > > + unsigned long uaddr, > > + unsigned long size); > > While we're at it, can we just convert this to the "two tabs" > indentation starting on second parameter line" way of doing things? Same > for all other cases. (at least in core code, if some arch wants their > own weird rules on how to handle these things) Sure. > > [...] > > > struct tlbflush_unmap_batch *tlb_ubc =3D ¤t->tlb_ubc; > > int batch; > > @@ -681,7 +682,7 @@ static void set_tlb_ubc_flush_pending(struct mm_str= uct *mm, pte_t pteval, > > if (!pte_accessible(mm, pteval)) > > return; > > > > - arch_tlbbatch_add_pending(&tlb_ubc->arch, mm, uaddr); > > + arch_tlbbatch_add_pending(&tlb_ubc->arch, mm, uaddr, size); > > tlb_ubc->flush_required =3D true; > > > > /* > > @@ -757,7 +758,8 @@ void flush_tlb_batched_pending(struct mm_struct *mm= ) > > } > > #else > > static void set_tlb_ubc_flush_pending(struct mm_struct *mm, pte_t pte= val, > > - unsigned long uaddr) > > + unsigned long uaddr, > > + unsigned long size) > > I'll note that mist tlb functions seem to consume start+end instead of > start+size, like > > flush_tlb_mm_range() > flush_tlb_kernel_range() > > So I'm wondering if this should be start+end instead of uaddr+size. For some reason, I can=E2=80=99t recall why I originally named it "uaddr" i= nstead of "address" at: https://lore.kernel.org/lkml/20220707125242.425242-4-21cnbao@gmail.com/ The name seems a bit odd now. It's probably because the arm64 functions listed below are using "uaddr": static inline void __flush_tlb_page_nosync(struct mm_struct *mm, unsigned long uaddr); static inline void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr); At that time, we only supported a single page for TLB deferred shootdown. Regarding set_tlb_ubc_flush_pending(), I=E2=80=99m fine with either approac= h: 1. start, size 2. start, end For option 1, it is eventually converted to (start, start + size) when call= ing __flush_tlb_range_nosync(). But if we convert to (start, end), it seems to align with static inline void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); So if there is no objection from Will, I will move to (start, end) in v3. > > -- > Cheers, > > David / dhildenb > Thanks Barry