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Wed, 22 Oct 2025 02:38:05 -0700 (PDT) MIME-Version: 1.0 References: <20251013092038.6963-1-ying.huang@linux.alibaba.com> <20251013092038.6963-3-ying.huang@linux.alibaba.com> <87a51jfl44.fsf@DESKTOP-5N7EMDA> <871pmv9unr.fsf@DESKTOP-5N7EMDA> <875xc78es0.fsf@DESKTOP-5N7EMDA> In-Reply-To: <875xc78es0.fsf@DESKTOP-5N7EMDA> From: Barry Song <21cnbao@gmail.com> Date: Wed, 22 Oct 2025 22:37:54 +1300 X-Gm-Features: AS18NWA2mUCn-m7yzg54mG9Xj4DEjFUtxQVduHJ8uk8kWT6HeuKAOvMULXrelik Message-ID: Subject: Re: [PATCH -v2 2/2] arm64, tlbflush: don't TLBI broadcast if page reused in write fault To: "Huang, Ying" Cc: Catalin Marinas , Will Deacon , Andrew Morton , David Hildenbrand , Lorenzo Stoakes , Vlastimil Babka , Zi Yan , Baolin Wang , Ryan Roberts , Yang Shi , "Christoph Lameter (Ampere)" , Dev Jain , Anshuman Khandual , Yicong Yang , Kefeng Wang , Kevin Brodsky , Yin Fengwei , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org Content-Type: text/plain; charset="UTF-8" X-Stat-Signature: 6hag8piqeh8gmfpfw6sof7pdmftg14tq X-Rspamd-Queue-Id: C9BFAC0010 X-Rspam-User: X-Rspamd-Server: rspam08 X-HE-Tag: 1761125886-737387 X-HE-Meta: U2FsdGVkX180je1xxW0ck+2IfoRYPAicowr0yO+ZPkmflf12Ki1LqnA/rnFpb9n5WieRHjPu+LyJztHfmL8TifKU3kLnbAREYSx1XMJx4igpWDFC9/8V0L6+khk3/wAwycjcs8DHAVySYuwzqO/nd87/KdskiumzlhGyy3Va6I7EY5/ylf+BSwH91ZeajGrUMNWGassJzGBUhUtdabJLt1JxtwHZiAeWQwRoShnn1XeO+F7Oy+3Imv5zCLCj9Y9Y/seEHrJf+b7U6r+wzdwT/1TcfksBkh1+THi1eAUD4jP/bJ7wYm9bM76kDDE2uhql0ZMtaZ/y783M3tW3x/SJsseGIqBk6iaViQdnA5TPX/Fdh6i2IXqNEQFxn7TaxKN2U5xujNn0TiLTiFhhysSwYuJO021eMyZA9FqJSlavM7Yvfo0ZTGKURnQoSFZAF3ztk8CleMROaFt9IMLTL10qGPKC+4rP7UgvIXnYHg5EaxoDfwPcG00vjz1XyqA6nXeJlWDT1QJjXo+2Zv1Bp2g9HLElV6z0DogFOFVEqg+qPKW8RHrThz6x+NYF/XcSg6CsNBcJ+Vq5gX1WJa+8PBEDER8YRAWVxre6jQlfJQJ8HPjk9PO5VWQyexBMwNnDvkjRfWPQrB1cgcEXlieusHgCz8eGDSHA7BveeSsIOHZCrseZrgD3xFpBzQaC0MAX+jQ//Q7q3ckXPn5a/Ndx6+AULjR+HkNdy1k40dqAMqbYDNfuJAsfr6rSTV0aB6qB9SAO21HT6/n6l0kUFndDOqcEO6k/9ouddx9JVUn6xIo75U1XAXx+n1CDRk/ZUF2lDJ/4GFDwamtGP/7pFUdhh9P1mHllLe7GTUPDjq6drFFhHTf8YzV1S9qrEhinBUTlQ05VoY99HEOTeeZvoHwmgGgRaGTkSH4OaQfW/H2pTtInkx8gGkZB/2/a2rZ+ZnschYnjGLBNM9Ny2TV4SvC4aTn 4EPAG33r 3Bv1HqCbvxUIWDuB41w4fz53IhKYWcRvlOKonYUx8APdSdc880O5c/70wsXcGYWWXLU1b1rXGvSxNLpd/Kw+Po9bXPa3OE3X+flvx0ya0WF1kpvl4d+QnpQ1MuMwVoqrQENzTfM0BCG90+rhsL+5wnA7u9/JwAVdvm7EpjFCYOCXiJ+Vo0fwj1jKfMXZ+ZNdxwW7xZk7fczKvFHyOEJs9GyCNN3vsuV2FWm4TqxiRs2rzcUw3gazJQWrwIOeZzKOhxj9aLaRtafdzOuKNiH/DjC0CeIEpC6Eo/B6buMdJahf9ynvkxK28BIn37rxlfPSPQr/BU0Td9OZqxF4tld8QGM2in8d6SS/7wHafUdCcjbHvNt8= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: > > With PTL, this becomes > > CPU0: CPU1: > > page fault page fault > lock PTL > write PTE > do local tlbi > unlock PTL > lock PTL <- pte visible to CPU 1 > read PTE <- new PTE > do local tlbi <- new PTE > unlock PTL I agree. Yet the ish barrier can still avoid the page faults during CPU0's PTL. CPU0: CPU1: lock PTL write pte; Issue ish barrier do local tlbi; No page fault occurs if tlb misses unlock PTL Otherwise, it could be: CPU0: CPU1: lock PTL write pte; Issue nsh barrier do local tlbi; page fault occurs if tlb misses unlock PTL Not quite sure if adding an ish right after the PTE modification has any noticeable performance impact on the test? I assume the most expensive part is still the tlbi broadcast dsb, not the PTE memory sync barrier? Thanks Barry