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Fri, 03 Jan 2025 09:50:24 -0800 (PST) MIME-Version: 1.0 References: <20241230175550.4046587-1-riel@surriel.com> <20241230175550.4046587-12-riel@surriel.com> In-Reply-To: <20241230175550.4046587-12-riel@surriel.com> From: Jann Horn Date: Fri, 3 Jan 2025 18:49:48 +0100 X-Gm-Features: AbW1kvaRIBdUEI7u8eWes6esOyGb6_zTS_gOkY_LYuLi88QF0ny_9OeFF9HTSbg Message-ID: Subject: Re: [PATCH 11/12] x86/mm: enable AMD translation cache extensions To: Rik van Riel Cc: x86@kernel.org, linux-kernel@vger.kernel.org, kernel-team@meta.com, dave.hansen@linux.intel.com, luto@kernel.org, peterz@infradead.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, akpm@linux-foundation.org, nadav.amit@gmail.com, zhengqi.arch@bytedance.com, linux-mm@kvack.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Rspamd-Queue-Id: D950240006 X-Stat-Signature: g1hzdk36eiap3xukbgp1ccc8gt94byqo X-Rspam-User: X-Rspamd-Server: rspam11 X-HE-Tag: 1735926570-384516 X-HE-Meta: U2FsdGVkX1/NzAyAIxj20LbWaMnYmi9znbmOyN3x1TK3qMUQm4TExsaTqgIFqWYgPNHpeodVvu6m3un3QUUkwSOP19XI8aitPY8sCL61yTxvETSgR1gBrpGiaDc2H7QCoGOTZn4WqhvDX2JAsDccnwZS0h8o3xfBdp+zDNSTYX9IG73HwCFxglEl4JiyBkiqYl0DGBJlmbEa/xxGXBJ6irN8s11P4LXf6w69tReQU7zeVi6bXl7TsfcxZAbcST2SI3nWL1pzTUWev/jaXM1vJH35ev2zxNB9oyowYPewIizOfuq73FZgb8SoKlQB8QqMRoy/N9QwV3LIiXJ4+7wCu6Pgxw7fu4zyUBiyvbiraLIp5OgvDr6xq+c3TMzjF3Pw67R9f8WdJX+6pnKNUNnrE6d6KQGycE8kHyCTK8EtiH3hOuT1Ml/29hOIE00eK0T6FI9b0OgH6hwNvjwVB5NIxDCd0+GCLdtUpCcgHclVOEqI4WFY2fz0+vSmKHZepjjLblCXbIfQ1JYCZyxBaQ4dZsPuGisoHFln2OYE66SjlFeL3vKmFoI16u394B8QFmgqqLHNUMIHV06iRLBdBzZFqQxErX3l6vk2LkPPczeABnLZW5vvzDrdSJBPUjV1pgeG4IC1Iv0mNQF08aQIIn0MwWhn757ut/z5/BSPfQzLf9GseuSk2T+F9IEKzi0ipUXRptIH/+zRneU7NJs6HcEsvKQcBMPi17RNz2gnkO9e5NA42FAoctv5Uy1wqJpaM7rYXEjidLMJslysFQyoqZXXo4lVAe/y0CaK9xX8C1B4O7y2Uzl/lJT41Vtuupki7Xe+7v8Vb8cCNHDburAPfq0BxM2iWmxzbCquzE/5mazCfpj8fdMjC0LJ2WITkYKQMINyTLQPJZxdkbdnQeDBL70XcDzeDxtPLIIqb11SeaFxjn1wKu9BdnetILZv+aUKmxZ4IQF+jq3pBAJdEUC0JML zuc7q8kg hxKKhDHoQdCD93g7BuFgqX5ReUHPFneTieDdS0IMgezLodtxe8Gq5oOmmGiyf6z19oJJy/LRSu7vrIxZL0+BYS+/s92DSIwIZ6Ck4KS/HJbW5of17zvz2H49t5uT+TGKK2e/H3BmEFTpQh9Daslm+/BdGXoIYmMryEnoRLb27h5j33WGXjgfWq7IhtCyzAMT0R3DqdcteEqOFiLSJNzwUVTPwnNimyeep3Pps3aGmVItzfT+ASBoESFlL87cUezwhkYoix66qJoBSqqpUJps5ZUj2ON9f2uQjoqfF16HHf8Ha10H4koJ8WRgT/JcJ56NmM9HabNDXhk31yx4= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000007, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: On Mon, Dec 30, 2024 at 6:53=E2=80=AFPM Rik van Riel wro= te: > With AMD TCE (translation cache extensions) only the intermediate mapping= s > that cover the address range zapped by INVLPG / INVLPGB get invalidated, > rather than all intermediate mappings getting zapped at every TLB invalid= ation. > > This can help reduce the TLB miss rate, by keeping more intermediate > mappings in the cache. > > >From the AMD manual: > > Translation Cache Extension (TCE) Bit. Bit 15, read/write. Setting this b= it > to 1 changes how the INVLPG, INVLPGB, and INVPCID instructions operate on > TLB entries. When this bit is 0, these instructions remove the target PTE > from the TLB as well as all upper-level table entries that are cached > in the TLB, whether or not they are associated with the target PTE. > When this bit is set, these instructions will remove the target PTE and > only those upper-level entries that lead to the target PTE in > the page table hierarchy, leaving unrelated upper-level entries intact. How does this patch interact with KVM SVM guests? In particular, will this patch cause TLB flushes performed by guest kernels to behave differently? [...] > diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c > index 454a370494d3..585d0731ca9f 100644 > --- a/arch/x86/mm/tlb.c > +++ b/arch/x86/mm/tlb.c > @@ -477,7 +477,7 @@ static void broadcast_tlb_flush(struct flush_tlb_info= *info) > if (info->stride_shift > PMD_SHIFT) > maxnr =3D 1; > > - if (info->end =3D=3D TLB_FLUSH_ALL) { > + if (info->end =3D=3D TLB_FLUSH_ALL || info->freed_tables) { > invlpgb_flush_single_pcid(kern_pcid(asid)); > /* Do any CPUs supporting INVLPGB need PTI? */ > if (static_cpu_has(X86_FEATURE_PTI)) > @@ -1110,7 +1110,7 @@ static void flush_tlb_func(void *info) > * > * The only question is whether to do a full or partial flush. > * > - * We do a partial flush if requested and two extra conditions > + * We do a partial flush if requested and three extra conditions > * are met: > * > * 1. f->new_tlb_gen =3D=3D local_tlb_gen + 1. We have an invari= ant that > @@ -1137,10 +1137,14 @@ static void flush_tlb_func(void *info) > * date. By doing a full flush instead, we can increase > * local_tlb_gen all the way to mm_tlb_gen and we can probably > * avoid another flush in the very near future. > + * > + * 3. No page tables were freed. If page tables were freed, a ful= l > + * flush ensures intermediate translations in the TLB get flus= hed. > */ Why is this necessary - do we ever issue TLB flushes that are intended to zap upper-level entries which are not covered by the specified address range? When, for example, free_pmd_range() gets rid of a page table, it calls pmd_free_tlb(), which sets tlb->freed_tables and does tlb_flush_pud_range(tlb, address, PAGE_SIZE).