From: Souptick Joarder <jrdr.linux@gmail.com>
To: Dan Carpenter <dan.carpenter@oracle.com>
Cc: kbuild@lists.01.org, Kashyap Desai <kashyap.desai@broadcom.com>,
kbuild test robot <lkp@intel.com>,
kbuild-all@lists.01.org,
Linux Memory Management List <linux-mm@kvack.org>,
"Martin K. Petersen" <martin.petersen@oracle.com>,
Hannes Reinecke <hare@suse.de>, Tomas Henzl <thenzl@redhat.com>,
Himanshu Madhani <himanshu.madhani@oracle.com>
Subject: Re: [linux-next:master 5384/13831] drivers/scsi/mpi3mr/mpi3mr_os.c:873 mpi3mr_update_tgtdev() error: we previously assumed 'mrioc->shost' could be null (see line 870)
Date: Tue, 6 Jul 2021 00:04:40 +0530 [thread overview]
Message-ID: <CAFqt6zao1p9Gg=eVLiB00Xp3gokR5+HZZBYAUSv09k2XKXqcXw@mail.gmail.com> (raw)
In-Reply-To: <202106282039.5z2USbJH-lkp@intel.com>
On Mon, Jun 28, 2021 at 5:59 PM Dan Carpenter <dan.carpenter@oracle.com> wrote:
>
> tree: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
> head: 3579aa488520feeda433ceca23ef4704bf8cd280
> commit: 74e1f30a28680978fa9ddfb5360d0cc644cd348e [5384/13831] scsi: mpi3mr: Add EEDP DIF DIX support
> config: i386-randconfig-m021-20210628 (attached as .config)
> compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
>
> If you fix the issue, kindly add following tag as appropriate
> Reported-by: kernel test robot <lkp@intel.com>
> Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
>
> smatch warnings:
> drivers/scsi/mpi3mr/mpi3mr_os.c:873 mpi3mr_update_tgtdev() error: we previously assumed 'mrioc->shost' could be null (see line 870)
>
> vim +873 drivers/scsi/mpi3mr/mpi3mr_os.c
>
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 800 static void mpi3mr_update_tgtdev(struct mpi3mr_ioc *mrioc,
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 801 struct mpi3mr_tgt_dev *tgtdev, struct mpi3_device_page0 *dev_pg0)
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 802 {
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 803 u16 flags = 0;
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 804 struct mpi3mr_stgt_priv_data *scsi_tgt_priv_data;
> 74e1f30a286809 Kashyap Desai 2021-05-20 805 u8 prot_mask = 0;
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 806
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 807 tgtdev->perst_id = le16_to_cpu(dev_pg0->persistent_id);
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 808 tgtdev->dev_handle = le16_to_cpu(dev_pg0->dev_handle);
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 809 tgtdev->dev_type = dev_pg0->device_form;
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 810 tgtdev->encl_handle = le16_to_cpu(dev_pg0->enclosure_handle);
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 811 tgtdev->parent_handle = le16_to_cpu(dev_pg0->parent_dev_handle);
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 812 tgtdev->slot = le16_to_cpu(dev_pg0->slot);
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 813 tgtdev->q_depth = le16_to_cpu(dev_pg0->queue_depth);
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 814 tgtdev->wwid = le64_to_cpu(dev_pg0->wwid);
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 815
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 816 flags = le16_to_cpu(dev_pg0->flags);
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 817 tgtdev->is_hidden = (flags & MPI3_DEVICE0_FLAGS_HIDDEN);
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 818
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 819 if (tgtdev->starget && tgtdev->starget->hostdata) {
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 820 scsi_tgt_priv_data = (struct mpi3mr_stgt_priv_data *)
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 821 tgtdev->starget->hostdata;
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 822 scsi_tgt_priv_data->perst_id = tgtdev->perst_id;
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 823 scsi_tgt_priv_data->dev_handle = tgtdev->dev_handle;
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 824 scsi_tgt_priv_data->dev_type = tgtdev->dev_type;
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 825 }
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 826
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 827 switch (tgtdev->dev_type) {
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 828 case MPI3_DEVICE_DEVFORM_SAS_SATA:
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 829 {
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 830 struct mpi3_device0_sas_sata_format *sasinf =
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 831 &dev_pg0->device_specific.sas_sata_format;
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 832 u16 dev_info = le16_to_cpu(sasinf->device_info);
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 833
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 834 tgtdev->dev_spec.sas_sata_inf.dev_info = dev_info;
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 835 tgtdev->dev_spec.sas_sata_inf.sas_address =
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 836 le64_to_cpu(sasinf->sas_address);
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 837 if ((dev_info & MPI3_SAS_DEVICE_INFO_DEVICE_TYPE_MASK) !=
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 838 MPI3_SAS_DEVICE_INFO_DEVICE_TYPE_END_DEVICE)
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 839 tgtdev->is_hidden = 1;
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 840 else if (!(dev_info & (MPI3_SAS_DEVICE_INFO_STP_SATA_TARGET |
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 841 MPI3_SAS_DEVICE_INFO_SSP_TARGET)))
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 842 tgtdev->is_hidden = 1;
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 843 break;
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 844 }
> 8e653455547a47 Kashyap Desai 2021-05-20 845 case MPI3_DEVICE_DEVFORM_PCIE:
> 8e653455547a47 Kashyap Desai 2021-05-20 846 {
> 8e653455547a47 Kashyap Desai 2021-05-20 847 struct mpi3_device0_pcie_format *pcieinf =
> 8e653455547a47 Kashyap Desai 2021-05-20 848 &dev_pg0->device_specific.pcie_format;
> 8e653455547a47 Kashyap Desai 2021-05-20 849 u16 dev_info = le16_to_cpu(pcieinf->device_info);
> 8e653455547a47 Kashyap Desai 2021-05-20 850
> 8e653455547a47 Kashyap Desai 2021-05-20 851 tgtdev->dev_spec.pcie_inf.capb =
> 8e653455547a47 Kashyap Desai 2021-05-20 852 le32_to_cpu(pcieinf->capabilities);
> 8e653455547a47 Kashyap Desai 2021-05-20 853 tgtdev->dev_spec.pcie_inf.mdts = MPI3MR_DEFAULT_MDTS;
> 8e653455547a47 Kashyap Desai 2021-05-20 854 /* 2^12 = 4096 */
> 8e653455547a47 Kashyap Desai 2021-05-20 855 tgtdev->dev_spec.pcie_inf.pgsz = 12;
> 8e653455547a47 Kashyap Desai 2021-05-20 856 if (dev_pg0->access_status == MPI3_DEVICE0_ASTATUS_NO_ERRORS) {
> 8e653455547a47 Kashyap Desai 2021-05-20 857 tgtdev->dev_spec.pcie_inf.mdts =
> 8e653455547a47 Kashyap Desai 2021-05-20 858 le32_to_cpu(pcieinf->maximum_data_transfer_size);
> 8e653455547a47 Kashyap Desai 2021-05-20 859 tgtdev->dev_spec.pcie_inf.pgsz = pcieinf->page_size;
> 8e653455547a47 Kashyap Desai 2021-05-20 860 tgtdev->dev_spec.pcie_inf.reset_to =
> 8e653455547a47 Kashyap Desai 2021-05-20 861 pcieinf->controller_reset_to;
> 8e653455547a47 Kashyap Desai 2021-05-20 862 tgtdev->dev_spec.pcie_inf.abort_to =
> 8e653455547a47 Kashyap Desai 2021-05-20 863 pcieinf->nv_me_abort_to;
> 8e653455547a47 Kashyap Desai 2021-05-20 864 }
> 8e653455547a47 Kashyap Desai 2021-05-20 865 if (tgtdev->dev_spec.pcie_inf.mdts > (1024 * 1024))
> 8e653455547a47 Kashyap Desai 2021-05-20 866 tgtdev->dev_spec.pcie_inf.mdts = (1024 * 1024);
> 8e653455547a47 Kashyap Desai 2021-05-20 867 if ((dev_info & MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_MASK) !=
> 8e653455547a47 Kashyap Desai 2021-05-20 868 MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_NVME_DEVICE)
> 8e653455547a47 Kashyap Desai 2021-05-20 869 tgtdev->is_hidden = 1;
> 74e1f30a286809 Kashyap Desai 2021-05-20 @870 if (mrioc->shost)
> ^^^^^^^^^^^^
> Check for NULL
>
> 74e1f30a286809 Kashyap Desai 2021-05-20 871 prot_mask = scsi_host_get_prot(mrioc->shost);
> 74e1f30a286809 Kashyap Desai 2021-05-20 872 if (prot_mask & SHOST_DIX_TYPE0_PROTECTION) {
> 74e1f30a286809 Kashyap Desai 2021-05-20 @873 scsi_host_set_prot(mrioc->shost, prot_mask & 0x77);
> ^^^^^^^^^^^^
> Do we need to check here as well?
I think, further check for NULL is not needed. Above check is sufficient.
>
> 74e1f30a286809 Kashyap Desai 2021-05-20 874 ioc_info(mrioc,
> 74e1f30a286809 Kashyap Desai 2021-05-20 875 "%s : Disabling DIX0 prot capability\n", __func__);
> 74e1f30a286809 Kashyap Desai 2021-05-20 876 ioc_info(mrioc,
> 74e1f30a286809 Kashyap Desai 2021-05-20 877 "because HBA does not support DIX0 operation on NVME drives\n");
> 74e1f30a286809 Kashyap Desai 2021-05-20 878 }
> 8e653455547a47 Kashyap Desai 2021-05-20 879 break;
> 8e653455547a47 Kashyap Desai 2021-05-20 880 }
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 881 case MPI3_DEVICE_DEVFORM_VD:
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 882 {
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 883 struct mpi3_device0_vd_format *vdinf =
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 884 &dev_pg0->device_specific.vd_format;
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 885
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 886 tgtdev->dev_spec.vol_inf.state = vdinf->vd_state;
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 887 if (vdinf->vd_state == MPI3_DEVICE0_VD_STATE_OFFLINE)
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 888 tgtdev->is_hidden = 1;
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 889 break;
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 890 }
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 891 default:
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 892 break;
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 893 }
> 13ef29ea4aa065 Kashyap Desai 2021-05-20 894 }
>
> ---
> 0-DAY CI Kernel Test Service, Intel Corporation
> https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
>
>
prev parent reply other threads:[~2021-07-05 18:34 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-28 12:29 Dan Carpenter
2021-07-05 18:34 ` Souptick Joarder [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='CAFqt6zao1p9Gg=eVLiB00Xp3gokR5+HZZBYAUSv09k2XKXqcXw@mail.gmail.com' \
--to=jrdr.linux@gmail.com \
--cc=dan.carpenter@oracle.com \
--cc=hare@suse.de \
--cc=himanshu.madhani@oracle.com \
--cc=kashyap.desai@broadcom.com \
--cc=kbuild-all@lists.01.org \
--cc=kbuild@lists.01.org \
--cc=linux-mm@kvack.org \
--cc=lkp@intel.com \
--cc=martin.petersen@oracle.com \
--cc=thenzl@redhat.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox