From: Pingfan Liu <kernelfans@gmail.com>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: x86@kernel.org, Michal Hocko <mhocko@suse.com>,
Dave Hansen <dave.hansen@linux.intel.com>,
Mike Rapoport <rppt@linux.ibm.com>,
Tony Luck <tony.luck@intel.com>,
Andy Lutomirski <luto@kernel.org>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
"H. Peter Anvin" <hpa@zytor.com>,
Andrew Morton <akpm@linux-foundation.org>,
Vlastimil Babka <vbabka@suse.cz>,
Oscar Salvador <osalvador@suse.de>,
Pavel Tatashin <pavel.tatashin@microsoft.com>,
Mel Gorman <mgorman@techsingularity.net>,
Benjamin Herrenschmidt <benh@kernel.crashing.org>,
Michael Ellerman <mpe@ellerman.id.au>,
Stephen Rothwell <sfr@canb.auug.org.au>, Qian Cai <cai@lca.pw>,
Barret Rhoden <brho@google.com>,
Bjorn Helgaas <bhelgaas@google.com>,
David Rientjes <rientjes@google.com>,
linux-mm@kvack.org, LKML <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 2/2] x86/numa: instance all parsed numa node
Date: Mon, 8 Jul 2019 16:36:23 +0800 [thread overview]
Message-ID: <CAFgQCTvwS+yEkAmCJnsCfnr0JS01OFtBnDg4cr41_GqU79A4Gg@mail.gmail.com> (raw)
In-Reply-To: <alpine.DEB.2.21.1907072133310.3648@nanos.tec.linutronix.de>
On Mon, Jul 8, 2019 at 3:44 AM Thomas Gleixner <tglx@linutronix.de> wrote:
>
> On Fri, 5 Jul 2019, Pingfan Liu wrote:
>
> > I hit a bug on an AMD machine, with kexec -l nr_cpus=4 option. nr_cpus option
> > is used to speed up kdump process, so it is not a rare case.
>
> But fundamentally wrong, really.
>
> The rest of the CPUs are in a half baken state and any broadcast event,
> e.g. MCE or a stray IPI, will result in a undiagnosable crash.
Very appreciate if you can pay more word on it? I tried to figure out
your point, but fail.
For "a half baked state", I think you concern about LAPIC state, and I
expand this point like the following:
For IPI: when capture kernel BSP is up, the rest cpus are still loop
inside crash_nmi_callback(), so there is no way to eject new IPI from
these cpu. Also we disable_local_APIC(), which effectively prevent the
LAPIC from responding to IPI, except NMI/INIT/SIPI, which will not
occur in crash case.
For MCE, I am not sure whether it can broadcast or not between cpus,
but as my understanding, it can not. Then is it a problem?
From another view point, is there any difference between nr_cpus=1 and
nr_cpus> 1 in crashing case? If stray IPI raises issue to nr_cpus>1,
it does for nr_cpus=1.
Thanks,
Pingfan
next prev parent reply other threads:[~2019-07-08 8:36 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-05 4:15 [PATCH 1/2] x86/numa: carve node online semantics out of alloc_node_data() Pingfan Liu
[not found] ` <1562300143-11671-2-git-send-email-kernelfans@gmail.com>
[not found] ` <alpine.DEB.2.21.1907072133310.3648@nanos.tec.linutronix.de>
2019-07-08 8:36 ` Pingfan Liu [this message]
[not found] ` <alpine.DEB.2.21.1907081125300.3648@nanos.tec.linutronix.de>
2019-07-08 17:53 ` [PATCH 2/2] x86/numa: instance all parsed numa node Andy Lutomirski
2019-07-09 4:26 ` Pingfan Liu
2019-07-09 4:16 ` Pingfan Liu
[not found] ` <alpine.DEB.2.21.1907090810490.1961@nanos.tec.linutronix.de>
[not found] ` <CAFgQCTui7D6_FQ_v_ijj6k_=+TQzQ3PaGvzxd6p+XEGjQ2S6jw@mail.gmail.com>
2019-07-09 13:34 ` Andy Lutomirski
2019-07-10 8:40 ` Pingfan Liu
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