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AJvYcCVh4klcK++pe4TX+Keu6xq+OZyObv4LUvxRjzxwt9jl6oqNiQo8jaO4iEvV6Ozn7e4R6dWJodZxtVmOMXEb/DI+0KY= X-Gm-Message-State: AOJu0YwqV9UecVf5D2lCv/m4b3nOYs1F+E+MsBdsP01YDYTi+nt3N9to rUOwvmWV5l4U7QrODDOBAFsYr/8Nsv3DnU4PSMFvtQAYpyDtKpfvhk2MzhjNpFGqmZaG9dfKkwH Yl3LH8qH46GNgO6rqzn1Th7cDltvTCbM6xgSEbQ== X-Google-Smtp-Source: AGHT+IFrg2HoG7q97DhSpbXNc25ham37J0pbg6a9qU7enuIB3n4fknfbf9j25G1aDzy1MVe4/zsyJcVd9XwGgb7dOzo= X-Received: by 2002:a05:6871:554:b0:222:7a41:b6a0 with SMTP id t20-20020a056871055400b002227a41b6a0mr1890669oal.6.1711520853082; Tue, 26 Mar 2024 23:27:33 -0700 (PDT) MIME-Version: 1.0 References: <20240327045035.368512-1-samuel.holland@sifive.com> <20240327045035.368512-9-samuel.holland@sifive.com> In-Reply-To: <20240327045035.368512-9-samuel.holland@sifive.com> From: yunhui cui Date: Wed, 27 Mar 2024 14:27:22 +0800 Message-ID: Subject: Re: [External] [PATCH v6 08/13] riscv: Avoid TLB flush loops when affected by SiFive CIP-1200 To: Samuel Holland Cc: Palmer Dabbelt , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, Alexandre Ghiti , Jisheng Zhang Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Rspamd-Queue-Id: 8A1151C0004 X-Rspam-User: X-Rspamd-Server: rspam04 X-Stat-Signature: xjzffr66it79n5i8765ysf7hrep6qu6x X-HE-Tag: 1711520855-750787 X-HE-Meta: U2FsdGVkX1+prjBHE0IxtcRatpYotSubTiqofXCKSc4pH7c95n5sduMOzgiMf2FL/zZDwe/TMpITOxtVhGkk9hScLEFNoBAlPivl6vvCGaCMi5+eSHYnNe9VL+Ks4H4/SsWcLvxLLD0Ox/R3nvYZbQerO0E5U4ws7roluo6QI3/VBRIMF3rAq/k/H5vqnRGjVYrLdI5WdfHUVwHsDFj2AehjV9ZmbA6pooRTPy+h9KqA7DumaGwaHe22026XTIuLoKiCfdkLZiTqISmjzdGeuTo6y0I4eP1F6SyBcupeYRtnSj4GqqEQ7oLtls2Lu3hJpvUmXLEHoDmh/pWgnWyioxbAiPkYWVxQZjG3dkkfdbOroSDPpa9HSUzSXxGxxwRbe3YwSTXkj1JvmTHNkYkc0FtTMmV+8bxXvIBXWGMKZZwo66KJags1OHYZUTjy7XIAkBa195DrecYuY7/Gfn25rH5P/rFZ3eaCraJiG+HeJY++VyzMnsHdckw8TRqdC3NOrpqgvHrgRd9aQ6XUdVk4VXoLZPO6qfu70d9diZAD58JIwUoVTgjl4G6MRQN3vR/thczIIum/DZF5bVNUSpH7eVdr8KifbmdYHdELZ9ZmO7BwLrEnOholjkgw6745GpfC15j0Ogq2V2uaMA1iXuC/CZwUufCgOOiClPN+ykXarDZl/soDicoiYPYO1M6iByDgTx93WGP3kq2/ThRVldz48wxpSW39HJeiUlg2wIqTqyYip4wZ9S8fHipblL72+GRRHOFCVMWpNPRPisL73YjEduuTqWAyh/g2ARda78Gj9zwc45Y1C/cSBzewcrltYXkQSDiESqYgl9vApnUTtOaKY0/bbikM4UFlbYfZbqzshJ7cCnBAppgylLuXXa9Lxg7KxW8Mw6Wj3BLhTWhqK6Vfz31QKUTm752x5Bd7+izlt3JfdHBARrEF9ItqsY4trV5jFlUgI5IRPfDQ1sDaYU/ CZKKI2Wo 7oYzjcClnNPJefpovKttWePc+CGTCsNicFC0oyYbIm0jDCAEuc/ImX0ggi6eEJCLqojNES577u7ZHrT5GWaui1zPOeQ6+gjlERCevabUtPsejyAJHlwVcjJTk4w7hJmktFKpeOd9o5xI5wnT9B/gZBL4M7o/6OOrXJYOO6FGcCsbWC1xxtLGyaeU1fJAipk9Fgm4jgopkj3XffdcUSRgTs9VI/DKAPS1P1KNl6GbKoGkuPWNybJyyFIs6MJ5wpogfaSXMGmkp1f/bPIP4+BFMQdltHNhUAHH7qx8medXuvhu0d9DGvcXDePZX9lOFSQxXE08lw1uAgM2tcJ32T8OUv+TycvFkMBZlSn9XIdY3heaSJmc= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Hi Samuel, On Wed, Mar 27, 2024 at 12:51=E2=80=AFPM Samuel Holland wrote: > > Implementations affected by SiFive errata CIP-1200 have a bug which > forces the kernel to always use the global variant of the sfence.vma > instruction. When affected by this errata, do not attempt to flush a > range of addresses; each iteration of the loop would actually flush the > whole TLB instead. Instead, minimize the overall number of sfence.vma > instructions. > > Signed-off-by: Samuel Holland > --- > > Changes in v6: > - Clarify the commit message for patch 8 based on ML discussion > > Changes in v4: > - Only set tlb_flush_all_threshold when CONFIG_MMU=3Dy. > > Changes in v3: > - New patch for v3 > > arch/riscv/errata/sifive/errata.c | 5 +++++ > arch/riscv/include/asm/tlbflush.h | 2 ++ > arch/riscv/mm/tlbflush.c | 2 +- > 3 files changed, 8 insertions(+), 1 deletion(-) > > diff --git a/arch/riscv/errata/sifive/errata.c b/arch/riscv/errata/sifive= /errata.c > index 3d9a32d791f7..716cfedad3a2 100644 > --- a/arch/riscv/errata/sifive/errata.c > +++ b/arch/riscv/errata/sifive/errata.c > @@ -42,6 +42,11 @@ static bool errata_cip_1200_check_func(unsigned long = arch_id, unsigned long imp > return false; > if ((impid & 0xffffff) > 0x200630 || impid =3D=3D 0x1200626) > return false; > + > +#ifdef CONFIG_MMU > + tlb_flush_all_threshold =3D 0; > +#endif > + > return true; > } > > diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/t= lbflush.h > index 463b615d7728..8e329721375b 100644 > --- a/arch/riscv/include/asm/tlbflush.h > +++ b/arch/riscv/include/asm/tlbflush.h > @@ -66,6 +66,8 @@ void arch_tlbbatch_add_pending(struct arch_tlbflush_unm= ap_batch *batch, > unsigned long uaddr); > void arch_flush_tlb_batched_pending(struct mm_struct *mm); > void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch); > + > +extern unsigned long tlb_flush_all_threshold; > #else /* CONFIG_MMU */ > #define local_flush_tlb_all() do { } while (0) > #endif /* CONFIG_MMU */ > diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c > index ad7bdcfcc219..18af7b5053af 100644 > --- a/arch/riscv/mm/tlbflush.c > +++ b/arch/riscv/mm/tlbflush.c > @@ -11,7 +11,7 @@ > * Flush entire TLB if number of entries to be flushed is greater > * than the threshold below. > */ > -static unsigned long tlb_flush_all_threshold __read_mostly =3D 64; > +unsigned long tlb_flush_all_threshold __read_mostly =3D 64; > > static void local_flush_tlb_range_threshold_asid(unsigned long start, > unsigned long size, > -- > 2.43.1 > Reviewed-by: Yunhui Cui Thanks, Yunhui