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AJvYcCX7oP+z6TfC0DLCVXLxNQl8MKRU6ogN21/SbLcNx+yZa5bXpT2+UBVaLHNO/Pyq2KCN1G92FUrXU4zYaMn2vMyyYjs= X-Gm-Message-State: AOJu0YwIkFzdi+AYZFv7P8z8DO5SoGoxUQk4y4zJs6UoS4H1UoAuiL3H xW33W2qyy4C8VBmMfO1Nl6pRKKyMpOEDJGG3PlthqnjjD88+3kNrltNXM9V5QWkxig1YdCsbjyZ 9mOdE7EwgRZgjvR6TCSzZyQCbJDUuoP3hNxeqyg== X-Google-Smtp-Source: AGHT+IEiTQS7oF0FArmnvNFhGVJ1tsGZOo1OMbhw60aKsqUYfW1SLdjZuDJW0kKZW//xD4oLw7aEds9MmsaU+EbtO1A= X-Received: by 2002:a05:6871:8e82:b0:220:bd1c:6c21 with SMTP id zq2-20020a0568718e8200b00220bd1c6c21mr98677oab.39.1709261336948; Thu, 29 Feb 2024 18:48:56 -0800 (PST) MIME-Version: 1.0 References: <20240229232211.161961-1-samuel.holland@sifive.com> <20240229232211.161961-9-samuel.holland@sifive.com> In-Reply-To: <20240229232211.161961-9-samuel.holland@sifive.com> From: yunhui cui Date: Fri, 1 Mar 2024 10:48:46 +0800 Message-ID: Subject: Re: [External] [PATCH v5 08/13] riscv: Avoid TLB flush loops when affected by SiFive CIP-1200 To: Samuel Holland Cc: Palmer Dabbelt , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, Alexandre Ghiti , Jisheng Zhang Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Rspamd-Queue-Id: DEE6340010 X-Rspam-User: X-Rspamd-Server: rspam11 X-Stat-Signature: c8mdxbhwkdzff8yb78nr8wnnnims8ayt X-HE-Tag: 1709261337-603737 X-HE-Meta: U2FsdGVkX19hgr3lI7PJ57i3LKQXBt+olXVl0he7WdCNls9OVEV5Rx9f0Ph/U/h6Q2SVrT3eKn1q3b8VewbNk9pMbNcJadw6/Tamliwf+diu1hUiJ9CF4QctP6ze+u+zjEX5e1A7ixr7OJYyHFQoioHNO01jNX1drfpREnaBb8PiV+N8SCp8ilPqoSMh7tTMhc3MRK9hyLfsCylUDew9QAiVkMJj3yFHAIYwoc71c//qzdKHp1BpXbiHSNIXNP+BqgbGc1z8UVoqWf5bt7sOoGpPd+oo8xnHBS7RVE3eHzlQcEX4klq/gpF9SFZrdAiNKqRbirWC2fCcPOZGo3cvl5RxAf5YMgUtwD2KUBdjxLGsvbXRsyERPJBEkTx8IwiSNFt9Ftmd1F7miOPRs8nBLxCQq9ccDWyKqO5L3Tl+z1/yD/0elwTBGkBadt0iYCZiARorMfJGqISCxSGWw0kv0BRyPR6PCYx/nSyY6d9n6GPBfW/hBzRf3AJUQhcnLBWcTH6VIVwym6dpRrMo2nWMwT945Dx/RYWuhbsyBm5TKWK4E5vp24N6HyrKVMOI0UtIlXz4+jtel4CVHzgcgm06/NAgpFEoUJCZHqFJg/hNSpw3ZMJSMABz5KkNbb/BlkMfVswFk/TFe2tsDD+UfnbhkKL+qQ3kc+udfqc2q5j6hykqhyJo3DtI3I0wI9/kXGbJWD65lffrYTmkZgINss88nPoVSCxpRA4OZCeOUQdBbyaAU4LkJ7tmMrQmFMS/ZkphAgEaXuFGFcprP7AMZhMkR/1OxDRA4dg0H8FTBXXzB0BNzHjpTO6XKMjH178PGEB04T91w04Snt3mspnzzfXf6nGYQqzWk5gbl5qEhldf+iMeQrtIEdS4tmFmkwskBq6KkcdYhp28pokmpHYWm5Y+PxF+qboY1gTmm8CEITcoU96b1fDDsmZzu2qAYM4MmkavMQCJMyh0I+g2jLkLNSC AxbC3fFn AyIY0X76aZnZPjBmG1+Z7ELqtNPKVVtZYaQAvlp3AgKiVtjgkadlk/F7seEpqA6GvHH4VhA76VE1pMYiF+Tb4VxJAtGxr4IW0hFMySOW3ArUyGi3Y6Qppmf7lD8dT/h36e1qivOTuQqfDDi9YOBwCAKxklnSMnN9ILf/2ddUJBuN33E0C5JIICw3y8PmoSgaI+VA5WIEbgIIqaOCiWunfqvDZ0tL/S0KmZNuBBTLCc4MzELE8Xh8jIRkyMt7vxovr2VRI/pX9WTsVN6haHUkA7pvjf5+wM44nsvf6O+cqhHTNvyE= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000008, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Hi Samuel, On Fri, Mar 1, 2024 at 7:22=E2=80=AFAM Samuel Holland wrote: > > Since implementations affected by SiFive errata CIP-1200 always use the > global variant of the sfence.vma instruction, they only need to execute > the instruction once. The range-based loop only hurts performance. > > Signed-off-by: Samuel Holland > --- > > (no changes since v4) > > Changes in v4: > - Only set tlb_flush_all_threshold when CONFIG_MMU=3Dy. > > Changes in v3: > - New patch for v3 > > arch/riscv/errata/sifive/errata.c | 5 +++++ > arch/riscv/include/asm/tlbflush.h | 2 ++ > arch/riscv/mm/tlbflush.c | 2 +- > 3 files changed, 8 insertions(+), 1 deletion(-) > > diff --git a/arch/riscv/errata/sifive/errata.c b/arch/riscv/errata/sifive= /errata.c > index 3d9a32d791f7..716cfedad3a2 100644 > --- a/arch/riscv/errata/sifive/errata.c > +++ b/arch/riscv/errata/sifive/errata.c > @@ -42,6 +42,11 @@ static bool errata_cip_1200_check_func(unsigned long = arch_id, unsigned long imp > return false; > if ((impid & 0xffffff) > 0x200630 || impid =3D=3D 0x1200626) > return false; > + > +#ifdef CONFIG_MMU > + tlb_flush_all_threshold =3D 0; > +#endif > + > return true; > } > > diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/t= lbflush.h > index 463b615d7728..8e329721375b 100644 > --- a/arch/riscv/include/asm/tlbflush.h > +++ b/arch/riscv/include/asm/tlbflush.h > @@ -66,6 +66,8 @@ void arch_tlbbatch_add_pending(struct arch_tlbflush_unm= ap_batch *batch, > unsigned long uaddr); > void arch_flush_tlb_batched_pending(struct mm_struct *mm); > void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch); > + > +extern unsigned long tlb_flush_all_threshold; > #else /* CONFIG_MMU */ > #define local_flush_tlb_all() do { } while (0) > #endif /* CONFIG_MMU */ > diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c > index 365e0a0e4725..22870f213188 100644 > --- a/arch/riscv/mm/tlbflush.c > +++ b/arch/riscv/mm/tlbflush.c > @@ -11,7 +11,7 @@ > * Flush entire TLB if number of entries to be flushed is greater > * than the threshold below. > */ > -static unsigned long tlb_flush_all_threshold __read_mostly =3D 64; > +unsigned long tlb_flush_all_threshold __read_mostly =3D 64; > > static void local_flush_tlb_range_threshold_asid(unsigned long start, > unsigned long size, > -- > 2.43.1 > If local_flush_tlb_all_asid() is used every time, more PTWs will be generated. Will such modifications definitely improve the overall performance? Hi Alex, Samuel, The relationship between flush_xx_range_asid() and nr_ptes is basically linear growth (y=3Dkx +b), while flush_all_asid() has nothing to do with nr_ptes (y=3Dc). Some TLBs may do some optimization. The operation of flush all itself requires very few cycles, but there is a certain delay between consecutive flush all. The intersection of the two straight lines is the optimal solution of tlb_flush_all_threshold. In actual situations, continuous flush_all_asid will not occur. One problem caused by flush_all_asid() is that multiple flush entries require PTW, which causes greater latency. Therefore, the value of tlb_flush_all_threshold needs to be considered or quantified. Maybe doing local_flush_tlb_page_asid() based on the actual nr_ptes_in_range would give better overall performance. What do you think? Thanks, Yunhui