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AJvYcCXiK9Y9ESVnWp4nl2jpHssVfvjN9BFdNhOCxV1WRFIlUopzgdUV6zAXy8WEq5xffJ8CbqLwUK3oJA==@kvack.org X-Gm-Message-State: AOJu0Yx4VJg/zTFeUR3ZcLUyPGp4tewP+1HUS6e9+xllL39/xS1oj7vO ZjyVjQpl0ox7EhADwS5zyaIRQhFi+pUbRZkOT3kHoB+BTRn7i42j2D71vBIugVLufYPS+2KTEoz VtX5e0cwLBi034RuUSPtUCFuL772TNhrL4WCz5zbbvw== X-Gm-Gg: ASbGnctPP/sOhNv9uo/Yp3viRRgxj+D9ZEYBBilvFXTQmGqq0yxLlYiHed0EhSMMNNv sbSPQCDXaKAvEG0HGh8pYVMRTaZQcdld8nsqIZsT5arruk4EUzXIDSLMBk8lBlGZOw3xo7DxouI o99esGK/kNHtBPTt/fA+zDoHIhHx4y88HXBKjGztvAeHJhJj9WjD3fbZTyzgpW8XDdjulhTn8mE mMgxy7MmCLKEwkV8A== X-Google-Smtp-Source: AGHT+IFb5FJ4SVuaW/MZYjqlxiCtjVdy/Gs9hCmULK5gWsYMbnHTDsvg0XfXKbqBDAFJs9xAYF0giEeS6uNYA+ao+FQ= X-Received: by 2002:a05:6512:3d11:b0:55f:65fc:8db5 with SMTP id 2adb3069b0e04-55f708b9c56mr3711945e87.23.1756851510074; Tue, 02 Sep 2025 15:18:30 -0700 (PDT) MIME-Version: 1.0 References: <20250902-pinctrl-gpio-pinfuncs-v7-0-bb091daedc52@linaro.org> In-Reply-To: <20250902-pinctrl-gpio-pinfuncs-v7-0-bb091daedc52@linaro.org> From: Linus Walleij Date: Wed, 3 Sep 2025 00:18:18 +0200 X-Gm-Features: Ac12FXw-1tPuaZxU9kVS8RfwbL5AeZ_YF1A5IdRwoR4crjvnC6JAL_oHeKPOKoA Message-ID: Subject: Re: [PATCH v7 00/16] pinctrl: introduce the concept of a GPIO pin function category To: Bartosz Golaszewski Cc: Bjorn Andersson , Konrad Dybcio , Alexey Klimov , Lorenzo Bianconi , Sean Wang , Matthias Brugger , AngeloGioacchino Del Regno , Paul Cercueil , Kees Cook , Andy Shevchenko , Andrew Morton , David Hildenbrand , Lorenzo Stoakes , "Liam R. Howlett" , Vlastimil Babka , Mike Rapoport , Suren Baghdasaryan , Michal Hocko , Dong Aisheng , Fabio Estevam , Shawn Guo , Jacky Bai , Pengutronix Kernel Team , NXP S32 Linux Team , Sascha Hauer , Tony Lindgren , Haojian Zhuang , Geert Uytterhoeven , Greg Kroah-Hartman , "Rafael J. Wysocki" , Danilo Krummrich , Neil Armstrong , Mark Brown , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mm@kvack.org, imx@lists.linux.dev, linux-omap@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Bartosz Golaszewski , stable@vger.kernel.org, Chen-Yu Tsai , Konrad Dybcio Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Rspamd-Server: rspam07 X-Rspamd-Queue-Id: 0BAEB40011 X-Stat-Signature: 8ci4p3fn366w1dxtbq9o81bcnj9d81fw X-Rspam-User: X-HE-Tag: 1756851511-430281 X-HE-Meta: U2FsdGVkX1+l6rIUCOuZhV7XrjhE7LL7iShtWU+YPDWlrufjkkxtUniSFvPVv8PmAD4mcUwQ6lYz1LrcbFF6z4J3uK44QYxu7bBMOhCnuMgmtCu7QxDSJN316rbQR+f1votOd7ghUuogpLaUsHTWnGQqFG+Bl7JqpphIeMAwTMij/rRmeYKncSPGgM2Qvq5J/fzj1itScHTQhqM5YYgIM+U95ctMLZaq9spNMG/UuSyZ0BhzBWLTQHhDFS+yGQ4/A7PhEY5Ixw1gnWV4ogy1l+sSqNVjz6rJJs169++5QCqLiDwSwldDQRXoFDU9RNbS8SGflcQuaHgep0il2HPWNIxY1/pqQZAw8eTz0y91ABXSf/oc2KT2RwwGP8mkfJc6mmSL7u52gbjnOPSZa8/tqCRt5j5PwMeXowcIMsvEAEJ1jD0dQHFFS1CGABCvn1W4PYysU9rlRk92ykoLvW+GnzshlkqGKcoRuaqSX8De1ezyjExRpxecsWE3Fc9CHD680TqcZzkiqMk+QH2RMGVSv37sWth63IvnFXkjJsmZCfrktLlgScb7Bjp0VpAEl3fKlSXmOdp8NpxI1uDPNK7icnQSJ5mTwMNwDYxpW3PrLMCV2t4yO1qLXYoFyrHNvN4KqJ4275TrUdbTATsmY2qHQhApqSfrCsx5seu6G4iB4ja9HyLa5uVb66VB4g5paCrrD5VONGIOhyNrve85GxGpqGFXjcmy+4mlsFwtW5Kpal5WdJIrKsDm8pD+O4KpzWyQwEzc4ut9Av6jrVCKLtzOUzx56vw5ADkmr9nqHKnVOdOhhFQocDyDkbDEOBi3GqkArsMHOFjhGHftYaV5NG0uhshOiqvr1pmD11mtqgoqOb9zuJQ7mSCtAeBj4g+SR5v+W/1lWI4AMGKG4dGd+IaEUWAq0ZPaOL/VXrDmuJ39cP5/+Uexa1ydNszZP+M52qR1OSVbqvtzMDPzhwVlM7k s6yhkSdn nxerFTE9V4T309ok8zmkOBdcF02P7BRSWLArBvh3t6T2CHpUL/jTm+5DP5v6lHPWstCBCaEACWn09bZDAboWkzfvn8kNqPMTPrfha2pnPh3fRjUpkyhlZHCde0IiRbsMCxVFro9zzGtknKPelYa6QX/Ciy/o4VblHqf39QX43ic3JYKbGsBaW+O6K+ehngmK1V32FKyTh2FuzFt3z0iKz/g3YlCO0s2Q70T1Uf016Ba3GobuH9/oW5ZDn6nhDz4c6XjhJ4I0fReOcEQQ= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: On Tue, Sep 2, 2025 at 1:59=E2=80=AFPM Bartosz Golaszewski = wrote: > We have many Qualcomm SoCs (and I can imagine it's a common pattern in > other platforms as well) where we mux a pin to "gpio" function using the > `pinctrl-X` property in order to configure bias or drive-strength and > then access it using the gpiod API. This makes it impossible to mark the > pin controller module as "strict". > > This series proposes to introduce a concept of a sub-category of > pinfunctions: GPIO functions where the above is not true and the pin > muxed as a GPIO can still be accessed via the GPIO consumer API even for > strict pinmuxers. This is what I want for pin control, and fixes an ages old issue that pin control has no intrinsic awareness of if a pin is muxed to a function providing GPIO. So patches applied! Any remaining code nitpicks can be fixed in-tree, I need this to be able to apply the much desired Broadcom STB driver, so this needs to go into -next now for cooking. I also want to strictify some drivers using this, bringing GPIO function awareness into them, which is a good thing! Yours, Linus Walleij