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AJvYcCXRx/sa5KQwTvTCFgGxrXLUO/og967yDkcihXTqVfylqzYk08MokVtHFWa8qVldsgwWvI0ealeL7K2NOh8Jo7IwvsY= X-Gm-Message-State: AOJu0YwmD9Zw7GZ6CdJt29taH9AOIYki1TXgE7+SVdQkR4/NrLlf7FzG e/6FCuUB4+Hc3qR8dZGN/zoezpCYXR+OS56WzHck9UF36l0rJ+ML8EaaFZX7kYDai+US+yU/YYF AEockT/J09DdPFFzmnyc0j2cCSo8uwTAcM+acyA== X-Google-Smtp-Source: AGHT+IHmVt3D1f9M2NJWrIBfKS+ywa2zQiwLNnWOiwr78hl/9CSscWihllGTFRw/No9gJ2WWzeLcgCWgz+43efCBLuQ= X-Received: by 2002:a05:690c:6902:b0:61b:df5:7871 with SMTP id 00721157ae682-62085c7bd51mr46770797b3.16.1715212877458; Wed, 08 May 2024 17:01:17 -0700 (PDT) MIME-Version: 1.0 References: <20240403234054.2020347-1-debug@rivosinc.com> <20240403234054.2020347-6-debug@rivosinc.com> In-Reply-To: <20240403234054.2020347-6-debug@rivosinc.com> From: Andy Chiu Date: Thu, 9 May 2024 08:00:00 +0800 Message-ID: Subject: Re: [PATCH v3 05/29] riscv: zicfiss / zicfilp enumeration To: Deepak Gupta Cc: paul.walmsley@sifive.com, rick.p.edgecombe@intel.com, broonie@kernel.org, Szabolcs.Nagy@arm.com, kito.cheng@sifive.com, keescook@chromium.org, ajones@ventanamicro.com, conor.dooley@microchip.com, cleger@rivosinc.com, atishp@atishpatra.org, alex@ghiti.fr, bjorn@rivosinc.com, alexghiti@rivosinc.com, samuel.holland@sifive.com, conor@kernel.org, linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-kselftest@vger.kernel.org, corbet@lwn.net, palmer@dabbelt.com, aou@eecs.berkeley.edu, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, oleg@redhat.com, akpm@linux-foundation.org, arnd@arndb.de, ebiederm@xmission.com, Liam.Howlett@oracle.com, vbabka@suse.cz, lstoakes@gmail.com, shuah@kernel.org, brauner@kernel.org, jerry.shih@sifive.com, hankuan.chen@sifive.com, greentime.hu@sifive.com, evan@rivosinc.com, xiao.w.wang@intel.com, charlie@rivosinc.com, apatel@ventanamicro.com, mchitale@ventanamicro.com, dbarboza@ventanamicro.com, sameo@rivosinc.com, shikemeng@huaweicloud.com, willy@infradead.org, vincent.chen@sifive.com, guoren@kernel.org, samitolvanen@google.com, songshuaishuai@tinylab.org, gerg@kernel.org, heiko@sntech.de, bhe@redhat.com, jeeheng.sia@starfivetech.com, cyy@cyyself.name, maskray@google.com, ancientmodern4@gmail.com, mathis.salmen@matsal.de, cuiyunhui@bytedance.com, bgray@linux.ibm.com, mpe@ellerman.id.au, baruch@tkos.co.il, alx@kernel.org, david@redhat.com, catalin.marinas@arm.com, revest@chromium.org, josh@joshtriplett.org, shr@devkernel.io, deller@gmx.de, omosnace@redhat.com, ojeda@kernel.org, jhubbard@nvidia.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Stat-Signature: x7hzkk8rbttqex3jc88c3dnecsfq5s1e X-Rspam-User: X-Rspamd-Server: rspam02 X-Rspamd-Queue-Id: 9F0B8C0002 X-HE-Tag: 1715212878-57884 X-HE-Meta: U2FsdGVkX1+GQJhThgnELVvNw1PJs1e1mTeLJULgScQMMmT986AW7Sgn3In3hBIcVhab/+D4gFuER4PKVt071ezFOtrSjUXDVXM71o5rbsieR4GIXU8l1vBwqNI0se3GZUlgB+aAkYtI+FNPmhFVAbP5Yw6Idw80v/mxJHG0fUua7aONiJcuVx7NviFFupRVShv0cuXXxrkkVhu8m9NfYcHfppx1xQxCZ85j20ARFKhL7vSUYhDQduLNqbN9Xc0+MYS9T1+2FLiVLRWyDX8Qqs+akVJHY9NOL8yLYd1hBwxuG4UEkcxXR7C2PbufItiAPSR5QcXo0pub5sxWkcirSEmSgyUmI88fYNToMbjUsk80q93AEAFX1agFFv90xHRl25yKLlyndO+VEj4lA3sKI3ZV3Vyc/kRT7Z3aUSUrAo90464apwpa8VW/DfJXNmaZqq6nVdidCioDIYu6VrjP0c4LIhOadryDOne2lmULJ9dvxKxZHlb0JbNRFQeJVip7jBIkxXObxK/iIxF15Kg0FaBjhlL7zBxeTRaPB2HOPGFKe1EEUSXtHosjmT29KnYkzxkIJjG+rymoGZjNiwFQCNksos/BzVeszL0azB+oVOCMIEyVArJ/iEE1Wt5wykFZN6AXiGO5JcOT8+sjOkWJIVolYpZxgRb0/D04oWcqG86Wf7HF6aeKoAuKvRjYfa2HKuvPE9joupo1CqRc/VYbTOa6IUZ9cAfng1i/6BOpy0qimYBvJZLEPRIBIoJfBapgqXqStdKpjkw40rdnwDqSqOxPtoXAuwS8Pqb4dZw429krawL1lLjbSh12G1oJm745+u+NsTGQKD3U5XvbfQ1lttWkPZw7Y0UXjrZQWwDkIEOM+D22tFDSHkTZpWwOXGwrdTKGmyCENVor8MdGjW45PlkYsNXAuvW18uZKv8DsYwojoGSrUpJSGcMoX9vSdk19YjOB4RKb4L+QVV6Pb7V kPYm2iaD YCvoPpGLW4VgaMxUiK7EgJjHhJZ4KUq4VwYB1Yj8M4fenR1C5BFgCVWGXSTG9BLqowQZJzf4CTcIIsF4i4IcqzgiPWMSjaGYBDKoZivAKpZG1GKtRrhQ+HaPldaHxbroTSLjJFyNtTrqn83S2LB7mBMpVnEdrNO7nBuitOnJaCJhAGwB7ttAiCMCYBxCV3HGBTZXwqwJvBc+/fxbZpA5Exm/a//Vljt3LB1sN7pHj3eDTKIrOPi1pTCLPRYfbdpV5YBzyKIINDBphrFr2Tgw9jiuKUwwbi6/BUVVERbd0Dq8HORfDolj5BVG0CEJprVH0ak0RjWgIxs838xnW0VnF6OAXTAJTDQ5wsvRSmbuyDTNa9Y8= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Hi Deepak, On Thu, Apr 4, 2024 at 7:41=E2=80=AFAM Deepak Gupta wr= ote: > > This patch adds support for detecting zicfiss and zicfilp. zicfiss and > zicfilp stands for unprivleged integer spec extension for shadow stack > and branch tracking on indirect branches, respectively. > > This patch looks for zicfiss and zicfilp in device tree and accordinlgy > lights up bit in cpu feature bitmap. Furthermore this patch adds detectio= n > utility functions to return whether shadow stack or landing pads are > supported by cpu. > > Signed-off-by: Deepak Gupta > --- > arch/riscv/include/asm/cpufeature.h | 13 +++++++++++++ > arch/riscv/include/asm/hwcap.h | 2 ++ > arch/riscv/include/asm/processor.h | 1 + > arch/riscv/kernel/cpufeature.c | 2 ++ > 4 files changed, 18 insertions(+) > > diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm= /cpufeature.h > index 0bd11862b760..f0fb8d8ae273 100644 > --- a/arch/riscv/include/asm/cpufeature.h > +++ b/arch/riscv/include/asm/cpufeature.h > @@ -8,6 +8,7 @@ > > #include > #include > +#include > #include > #include > #include > @@ -137,4 +138,16 @@ static __always_inline bool riscv_cpu_has_extension_= unlikely(int cpu, const unsi > > DECLARE_STATIC_KEY_FALSE(fast_misaligned_access_speed_key); > > +static inline bool cpu_supports_shadow_stack(void) > +{ > + return (IS_ENABLED(CONFIG_RISCV_USER_CFI) && > + riscv_cpu_has_extension_unlikely(smp_processor_id(), = RISCV_ISA_EXT_ZICFISS)); > +} > + > +static inline bool cpu_supports_indirect_br_lp_instr(void) > +{ > + return (IS_ENABLED(CONFIG_RISCV_USER_CFI) && > + riscv_cpu_has_extension_unlikely(smp_processor_id(), = RISCV_ISA_EXT_ZICFILP)); > +} > + > #endif > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwca= p.h > index 1f2d2599c655..74b6c727f545 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -80,6 +80,8 @@ > #define RISCV_ISA_EXT_ZFA 71 > #define RISCV_ISA_EXT_ZTSO 72 > #define RISCV_ISA_EXT_ZACAS 73 nit: two tabs for alignment > +#define RISCV_ISA_EXT_ZICFILP 74 > +#define RISCV_ISA_EXT_ZICFISS 75 > > #define RISCV_ISA_EXT_XLINUXENVCFG 127 > > diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/= processor.h > index a8509cc31ab2..6c5b3d928b12 100644 > --- a/arch/riscv/include/asm/processor.h > +++ b/arch/riscv/include/asm/processor.h > @@ -13,6 +13,7 @@ > #include > > #include > +#include > > #ifdef CONFIG_64BIT > #define DEFAULT_MAP_WINDOW (UL(1) << (MMAP_VA_BITS - 1)) > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeatur= e.c > index 79a5a35fab96..d052cad5b82f 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -263,6 +263,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { > __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h), > __RISCV_ISA_EXT_SUPERSET(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xlin= uxenvcfg_exts), > __RISCV_ISA_EXT_SUPERSET(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xlin= uxenvcfg_exts), > + __RISCV_ISA_EXT_SUPERSET(zicfilp, RISCV_ISA_EXT_ZICFILP, riscv_xl= inuxenvcfg_exts), > + __RISCV_ISA_EXT_SUPERSET(zicfiss, RISCV_ISA_EXT_ZICFISS, riscv_xl= inuxenvcfg_exts), > __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR), > __RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND), > __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR), > -- > 2.43.2 > Thanks, Andy