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Wed, 04 Oct 2023 10:16:56 -0700 (PDT) MIME-Version: 1.0 References: <20230921-th1520-mmc-v1-0-49f76c274fb3@baylibre.com> In-Reply-To: From: "Lad, Prabhakar" Date: Wed, 4 Oct 2023 18:16:01 +0100 Message-ID: Subject: Re: [PATCH 0/6] RISC-V: Add eMMC support for TH1520 boards To: Robin Murphy Cc: Geert Uytterhoeven , Arnd Bergmann , Icenowy Zheng , Jisheng Zhang , Drew Fustini , Christoph Hellwig , Lad Prabhakar , Robert Nelson , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Adrian Hunter , Guo Ren , Fu Wei , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Jason Kridner , Xi Ruoyao , Han Gao , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, =?UTF-8?B?QmrDtnJuIFTDtnBlbA==?= , Alexandre Ghiti , Linux-MM , Fabrizio Castro Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Rspamd-Server: rspam09 X-Rspamd-Queue-Id: C1AC1C0016 X-Stat-Signature: eepwicm6jueb17bpmw1oz5q6rfnh9wjw X-Rspam-User: X-HE-Tag: 1696439817-465197 X-HE-Meta: U2FsdGVkX1+6T6X8YWU6mhpR84CBAY07P9IyIDUWpBAaZtYMNiilSICZxjTEXQBCIhfDOXMe5/phfPJ7DwZjG0JAB5u1v6Nb1+9nObINivClkwgMIk/Fld+B4KVXnBKTqZKCseb2y1YyWh9pWGYjExEbzlUtAwcvQZ5S6mKrWHuHdscS3EpLyvGf1Fu1/Z4DURaFo2rRybi6Y8Axzqq2wn+59SpopNKrEk+kFIAMi2XmVsxwQAjxHqBne8Eqy0ZmHtQokrJZHN1PRYtLSmT9CrhxH0tcA2RHXxoHt9zaYnMsTx1vbAw5jaFZ0QzaF2533gNEe8ZM42Jm3gUbVpjj5FnVHuemdkQW+weUzRXJsIIP6iHvm+AYYrkTIpe9+TQ7Khyxvh+bg0Jwd/DGQ+p57JJoC1gcIhbArmU521xrmTUU4Zll0+pTr+Wc/+kT/nO5R+NU5GYj6pmJXooTK0mw/7oJmwLQklw3U5iPBMzb9K6VNGAACVgCQts3An6RsV7JyWiXKrc/VQyHix/G+cGCCFZxvCddI/3aZ7LR0yFRw/tfhyZ5VZlWqn2O+0lFAfEmoHoXS7rfaIOvpi8d3AsaLeYpGYypD9SWHJTi9WuUJCFQfeAIJtyPqszQe+ws7JUFHX803qDcYL4TBGFMSSGhf5/rdUKHKHGNNUw3jaNPnbWKGMbNLTngcX11iKISo1yFR3Ab82CC43pWUhdNiqj5vUs1xq9jQcqVpaHs8H7FZKkVT0uVKUMCnOVbs79IywXb/bXQR6FtxXtfb5UPGzZtmzAT2Y58aKbMziqWw80MLqO5Q8XjT37Lzxs2VwAYvi6lbZ4gExT1nR2QbIbpOFPMI+21xSca6uoAwqecr3ZrNBay6r4q3QNVL+ofyV0pQ3E3uo8CU7AD7Jo3nLJYpRddoAovXpC6wh4ERhu6dDovCIJA8sVNIB8zuIEwxKlYH5fzq4f67mupr4/dS1Cr7cs gy/sMSjz GLUpfUO+u5lIEYw2/fkzq/+u0R4K1CGHNan/N9BziJAuDBzBMUA01hDJ40aPcVXfnKF82m5lqDXBMocWTsLuxE2THo/owQSwF+u8hohswy+zCItyqsqTRTNHm3tv4R+kEoCrIDuVWxiY6EtRdte+0XDG6L7IW905xMWiPREODpQMsmr378/ymwQoOnupRo5EjRrmlthC0mt+hmswodDFXfpXx7+6Ya1q0HN2V5hNQnXkDGfTTSQSEoa+WOeuLDFwG6Hm0A7eYhPE724hQNGQKEyISdmr47faRYfx8s+coy/lahdgnKso+ox2nl56TH1muPP6E/Q8lWQNjMmLUU+LKorKfiA9EpRXhpg1xemxRtKFKPhqHX2WQcvK6a9tZdOdXBpO9ym2WQn1NGghbzR9PN8oa6j82kjvc18Zf9/LsjOFRKdvgJPgoRY2cfwwOBamhY/TFbgx02alO9i6eAQGEPatjsdkxQfGCtj2AeD1fi9XkfDmXdSRTiYIsti6h/gZw0/WH6dFsnFFPrkKskGWBDeoDr/ea7YUJyN/PKU16tRmcDoxrR5l1dpM2PoP0DVliI0tKkT85hdy/+MNMTMVofQEHdMrdsPSE9exdl9o4tONMIeA= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On Wed, Oct 4, 2023 at 5:03=E2=80=AFPM Lad, Prabhakar wrote: > > On Wed, Oct 4, 2023 at 3:18=E2=80=AFPM Robin Murphy wrote: > > > > On 04/10/2023 3:02 pm, Icenowy Zheng wrote: > > [...] > > >>>> I believe commit 484861e09f3e ("soc: renesas: Kconfig: Select the > > >>>> required configs for RZ/Five SoC") can cause regression on all > > >>>> non-dma-coherent riscv platforms with generic defconfig. This is > > >>>> a common issue. The logic here is: generic riscv defconfig > > >>>> selects > > >>>> ARCH_R9A07G043 which selects DMA_GLOBAL_POOL, which assumes all > > >>>> non-dma-coherent riscv platforms have a dma global pool, this > > >>>> assumption > > >>>> seems not correct. And I believe DMA_GLOBAL_POOL should not be > > >>>> selected by ARCH_SOCFAMILIY, instead, only ARCH under some > > >>>> specific > > >>>> conditions can select it globaly, for example NOMMU ARM and so > > >>>> on. > > >>>> > > >>>> Since this is a regression, what's proper fix? any suggestion is > > >>>> appreciated. > > >> > > >> I think the answer is to not select DMA_GLOBAL_POOL, since that is > > >> only > > > > > > Well I think for RISC-V, it's not NOMMU only but applicable for every > > > core that does not support Svpbmt or vendor-specific alternatives, > > > because the original RISC-V priv spec does not define memory attribut= es > > > in page table entries. > > > > > > For the Renesas/Andes case I think a pool is set by OpenSBI with > > > vendor-specific M-mode facility and then passed in DT, and the S-mode > > > (which MMU is enabled in) just sees fixed memory attributes, in this > > > case I think DMA_GLOBAL_POOL is needed. > > > > Oh wow, is that really a thing? In that case, either you just can't > > support this platform in a multi-platform kernel, or someone needs to d= o > > some fiddly work in dma-direct to a) introduce the notion of an optiona= l > > global pool, > Looking at the code [0] we do have compile time check for > CONFIG_DMA_GLOBAL_POOL irrespective of this being present in DT or > not, instead if we make it compile time and runtime check ie either > check for DT node or see if pool is available and only then proceed > for allocation form this pool. > > What are your thoughts on this? > Something like the below: diff --git a/include/linux/dma-map-ops.h b/include/linux/dma-map-ops.h index f2fc203fb8a1..7bf41a4634a4 100644 --- a/include/linux/dma-map-ops.h +++ b/include/linux/dma-map-ops.h @@ -198,6 +198,7 @@ int dma_release_from_global_coherent(int order, void *vaddr); int dma_mmap_from_global_coherent(struct vm_area_struct *vma, void *cpu_ad= dr, size_t size, int *ret); int dma_init_global_coherent(phys_addr_t phys_addr, size_t size); +bool dma_global_pool_available(void); #else static inline void *dma_alloc_from_global_coherent(struct device *dev, ssize_t size, dma_addr_t *dma_handle) @@ -213,6 +214,10 @@ static inline int dma_mmap_from_global_coherent(struct vm_area_struct *vma, { return 0; } +static inline bool dma_global_pool_available(void) +{ + return false; +} #endif /* CONFIG_DMA_GLOBAL_POOL */ /* diff --git a/kernel/dma/coherent.c b/kernel/dma/coherent.c index c21abc77c53e..605f243b8262 100644 --- a/kernel/dma/coherent.c +++ b/kernel/dma/coherent.c @@ -277,6 +277,14 @@ int dma_mmap_from_dev_coherent(struct device *dev, struct vm_area_struct *vma, #ifdef CONFIG_DMA_GLOBAL_POOL static struct dma_coherent_mem *dma_coherent_default_memory __ro_after_ini= t; +bool dma_global_pool_available(void) +{ + if (!dma_coherent_default_memory) + return false; + + return true; +} + void *dma_alloc_from_global_coherent(struct device *dev, ssize_t size, dma_addr_t *dma_handle) { diff --git a/kernel/dma/direct.c b/kernel/dma/direct.c index 9596ae1aa0da..a599bb731ceb 100644 --- a/kernel/dma/direct.c +++ b/kernel/dma/direct.c @@ -235,7 +235,7 @@ void *dma_direct_alloc(struct device *dev, size_t size, * If there is a global pool, always allocate from it for * non-coherent devices. */ - if (IS_ENABLED(CONFIG_DMA_GLOBAL_POOL)) + if (IS_ENABLED(CONFIG_DMA_GLOBAL_POOL) && dma_global_pool_available()) return dma_alloc_from_global_coherent(dev, size, dma_handle); Cheers, Prabhakar > [0] https://elixir.bootlin.com/linux/v6.6-rc4/source/kernel/dma/direct.c#= L238 > > > and b) make it somehow cope with DMA_DIRECT_REMAP being > > enabled but non-functional. > > > DMA_DIRECT_REMAP config option is selected by NONCOHERENET config option = anyway. > > Cheers, > Prabhakar