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Tue, 19 Sep 2023 05:09:45 -0700 (PDT) MIME-Version: 1.0 References: <20230911131224.61924-1-alexghiti@rivosinc.com> <20230911131224.61924-4-alexghiti@rivosinc.com> In-Reply-To: <20230911131224.61924-4-alexghiti@rivosinc.com> From: "Lad, Prabhakar" Date: Tue, 19 Sep 2023 13:09:18 +0100 Message-ID: Subject: Re: [PATCH v4 3/4] riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlb To: Alexandre Ghiti Cc: Will Deacon , "Aneesh Kumar K . V" , Andrew Morton , Nick Piggin , Peter Zijlstra , Mayuresh Chitale , Vincent Chen , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-arch@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Samuel Holland , Andrew Jones Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Rspamd-Server: rspam09 X-Rspamd-Queue-Id: 6038040013 X-Stat-Signature: am47xexhcydjp4s43n5npg5ufac6zqja X-Rspam-User: X-HE-Tag: 1695125386-549139 X-HE-Meta: U2FsdGVkX1/JZ8SQOg6FL0EvNFt3F/Gce5z7ZWI+s4LiNes8NrdoKybBhdQbc5nkS/UvBQGnjjet6p43xa8huQtD4L3fan+DGkvQUlG1ya2aonVUS2a64ON7yrN8492+2DI7jv4j+8uVfx3cbs3C1tcsJYbmqRSGiaGnll70SpjZjeop5GkG6n3I3/XthVFapAKBcRUoQ8bnL97cPRpiUFYgUM3q/fFSqk7HTQb5IIruBjXo1K09ItAg6f8e64TWhlpiee6tJqlZkiPDGMa3aF7+kUOqz4fzlacARICcCTsJy9YDz5yIAx04+QbyxjZa8OhEwEc+O+8+zSukq97XYWAssJyLx8609dCzHUxfY4Km5GdbLZ1TNPiE8uZ1uDqnFJOT5G8FzIE3EjYHf4g8r6xV97RiilrSEt1FEYjUWDqf/M775kjg+7bgNoN3nyPwNvcCzUwHq7SPAdz1LXvZF1ok+WwvhceIUzmguSww3Xa3ovovG7/q2ceP9yHV2p8nfMPYwQYW3GDaP4U9u5iNwTCnwYT7d0K89omhW6lFEFfDlwQF+mCBLjtHPJsYjr7NWilqve2lN/4/NZXqjFAYqE1KOEqnnzU7RYnGnqWkZcwOO41eBvLNOMqmlK6xblD/dEQ6VMRiAIySyjp+1hmTqlyxXOqic0P9BDhiJrahEpkkhr99t9IbWOb8QbxLtIT0FmOsacUKuZoD6aEPzUg9emdJv8+TrJkko3GcXC5LAX4ROWSlYSJ4dpAkhVJ1W7iRv73jEtAJh3d89In6NH63Jf1Thkbjut2eeNkjDHz9CL7xtBJmz/PSMY6Sy8gCIWaY/CBnPynghlSMsJsWNRzk7xrjiMg0wQS6i6yv4qVsy5o307kXLYECQf8c9GFvE/tNPaGr1JaaQTngjnLWr7Ne0nCUk5B9EeUjrmBdf8ukkEPmBZx6DhlYMTJwdkX9b5QKec/yNriXO8S91f/T/DR pY3rGBiz LOCmIBIdNcRYRuQilPwncZ8Y33iQytaTRkRIh6NM4sH6ImXKsfDrcg5HUpOnhBrteEwRcSA60BlqJa9kO95SCRW30jSlzs29IIcqOapjd4sgcalnsQypGNLTkakVBM1JKSzLw3DKxMd2RESTanjwJo4EFS72aPamCksPp0KV6N13+o8tj3v//cbUDNbd2D8ZExEdqiGR+4upTS66FQ7KMQ4d6zdCqRuW0JaPWjYuUTraKpRaTukppzeMKNA7MBr5VNilXmP/UA1+4jI8jhKjm2gcEPiirhFDqXm4MBz3jh3d4/xyugStv+/N11IMnbcsp3sq6/ySVeVUjH2uKi96MLrjjrij8Dtv/soooXEM+aJRDML4FoPVjTOyZy4FZr7HrLohpb9udMhMDDYGZ4qShNc+jJ0ztWgnFh1wERxU7qAWbMIfTg+I/6pC2gNdqq88AEEmFpSUoWfkX8Ax7gzzD/yrQ/V3dpXMJBL6HRVH1brJ/iakEs7FZroFiBc5YYUh6KwaQW03ctfHqaF1jIpOdsHCY+SFfnbJGKqZUw+AB15xcfvOWQPHubX+8IxOdYJ2/STmVviT4LbEASs0= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On Mon, Sep 11, 2023 at 2:15=E2=80=AFPM Alexandre Ghiti wrote: > > Currently, when the range to flush covers more than one page (a 4K page o= r > a hugepage), __flush_tlb_range() flushes the whole tlb. Flushing the whol= e > tlb comes with a greater cost than flushing a single entry so we should > flush single entries up to a certain threshold so that: > threshold * cost of flushing a single entry < cost of flushing the whole > tlb. > > Co-developed-by: Mayuresh Chitale > Signed-off-by: Mayuresh Chitale > Signed-off-by: Alexandre Ghiti > Reviewed-by: Andrew Jones > --- > arch/riscv/include/asm/sbi.h | 3 - > arch/riscv/include/asm/tlbflush.h | 3 + > arch/riscv/kernel/sbi.c | 32 +++------ > arch/riscv/mm/tlbflush.c | 115 +++++++++++++++--------------- > 4 files changed, 72 insertions(+), 81 deletions(-) > Tested-by: Lad Prabhakar # On RZ/Five SMARC Cheers, Prabhakar > diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h > index 5b4a1bf5f439..b79d0228144f 100644 > --- a/arch/riscv/include/asm/sbi.h > +++ b/arch/riscv/include/asm/sbi.h > @@ -273,9 +273,6 @@ void sbi_set_timer(uint64_t stime_value); > void sbi_shutdown(void); > void sbi_send_ipi(unsigned int cpu); > int sbi_remote_fence_i(const struct cpumask *cpu_mask); > -int sbi_remote_sfence_vma(const struct cpumask *cpu_mask, > - unsigned long start, > - unsigned long size); > > int sbi_remote_sfence_vma_asid(const struct cpumask *cpu_mask, > unsigned long start, > diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/t= lbflush.h > index f5c4fb0ae642..170a49c531c6 100644 > --- a/arch/riscv/include/asm/tlbflush.h > +++ b/arch/riscv/include/asm/tlbflush.h > @@ -11,6 +11,9 @@ > #include > #include > > +#define FLUSH_TLB_MAX_SIZE ((unsigned long)-1) > +#define FLUSH_TLB_NO_ASID ((unsigned long)-1) > + > #ifdef CONFIG_MMU > extern unsigned long asid_mask; > > diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c > index c672c8ba9a2a..5a62ed1da453 100644 > --- a/arch/riscv/kernel/sbi.c > +++ b/arch/riscv/kernel/sbi.c > @@ -11,6 +11,7 @@ > #include > #include > #include > +#include > > /* default SBI version is 0.1 */ > unsigned long sbi_spec_version __ro_after_init =3D SBI_SPEC_VERSION_DEFA= ULT; > @@ -376,32 +377,15 @@ int sbi_remote_fence_i(const struct cpumask *cpu_ma= sk) > } > EXPORT_SYMBOL(sbi_remote_fence_i); > > -/** > - * sbi_remote_sfence_vma() - Execute SFENCE.VMA instructions on given re= mote > - * harts for the specified virtual address rang= e. > - * @cpu_mask: A cpu mask containing all the target harts. > - * @start: Start of the virtual address > - * @size: Total size of the virtual address range. > - * > - * Return: 0 on success, appropriate linux error code otherwise. > - */ > -int sbi_remote_sfence_vma(const struct cpumask *cpu_mask, > - unsigned long start, > - unsigned long size) > -{ > - return __sbi_rfence(SBI_EXT_RFENCE_REMOTE_SFENCE_VMA, > - cpu_mask, start, size, 0, 0); > -} > -EXPORT_SYMBOL(sbi_remote_sfence_vma); > - > /** > * sbi_remote_sfence_vma_asid() - Execute SFENCE.VMA instructions on giv= en > - * remote harts for a virtual address range belonging to a specific ASID= . > + * remote harts for a virtual address range belonging to a specific ASID= or not. > * > * @cpu_mask: A cpu mask containing all the target harts. > * @start: Start of the virtual address > * @size: Total size of the virtual address range. > - * @asid: The value of address space identifier (ASID). > + * @asid: The value of address space identifier (ASID), or FLUSH_TLB_NO_= ASID > + * for flushing all address spaces. > * > * Return: 0 on success, appropriate linux error code otherwise. > */ > @@ -410,8 +394,12 @@ int sbi_remote_sfence_vma_asid(const struct cpumask = *cpu_mask, > unsigned long size, > unsigned long asid) > { > - return __sbi_rfence(SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID, > - cpu_mask, start, size, asid, 0); > + if (asid =3D=3D FLUSH_TLB_NO_ASID) > + return __sbi_rfence(SBI_EXT_RFENCE_REMOTE_SFENCE_VMA, > + cpu_mask, start, size, 0, 0); > + else > + return __sbi_rfence(SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID= , > + cpu_mask, start, size, asid, 0); > } > EXPORT_SYMBOL(sbi_remote_sfence_vma_asid); > > diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c > index 5bda6d4fed90..2c1136d73411 100644 > --- a/arch/riscv/mm/tlbflush.c > +++ b/arch/riscv/mm/tlbflush.c > @@ -9,28 +9,50 @@ > > static inline void local_flush_tlb_all_asid(unsigned long asid) > { > - __asm__ __volatile__ ("sfence.vma x0, %0" > - : > - : "r" (asid) > - : "memory"); > + if (asid !=3D FLUSH_TLB_NO_ASID) > + __asm__ __volatile__ ("sfence.vma x0, %0" > + : > + : "r" (asid) > + : "memory"); > + else > + local_flush_tlb_all(); > } > > static inline void local_flush_tlb_page_asid(unsigned long addr, > unsigned long asid) > { > - __asm__ __volatile__ ("sfence.vma %0, %1" > - : > - : "r" (addr), "r" (asid) > - : "memory"); > + if (asid !=3D FLUSH_TLB_NO_ASID) > + __asm__ __volatile__ ("sfence.vma %0, %1" > + : > + : "r" (addr), "r" (asid) > + : "memory"); > + else > + local_flush_tlb_page(addr); > } > > -static inline void local_flush_tlb_range(unsigned long start, > - unsigned long size, unsigned long stride) > +/* > + * Flush entire TLB if number of entries to be flushed is greater > + * than the threshold below. > + */ > +static unsigned long tlb_flush_all_threshold __read_mostly =3D 64; > + > +static void local_flush_tlb_range_threshold_asid(unsigned long start, > + unsigned long size, > + unsigned long stride, > + unsigned long asid) > { > - if (size <=3D stride) > - local_flush_tlb_page(start); > - else > - local_flush_tlb_all(); > + u16 nr_ptes_in_range =3D DIV_ROUND_UP(size, stride); > + int i; > + > + if (nr_ptes_in_range > tlb_flush_all_threshold) { > + local_flush_tlb_all_asid(asid); > + return; > + } > + > + for (i =3D 0; i < nr_ptes_in_range; ++i) { > + local_flush_tlb_page_asid(start, asid); > + start +=3D stride; > + } > } > > static inline void local_flush_tlb_range_asid(unsigned long start, > @@ -38,8 +60,10 @@ static inline void local_flush_tlb_range_asid(unsigned= long start, > { > if (size <=3D stride) > local_flush_tlb_page_asid(start, asid); > - else > + else if (size =3D=3D FLUSH_TLB_MAX_SIZE) > local_flush_tlb_all_asid(asid); > + else > + local_flush_tlb_range_threshold_asid(start, size, stride,= asid); > } > > static void __ipi_flush_tlb_all(void *info) > @@ -52,7 +76,7 @@ void flush_tlb_all(void) > if (riscv_use_ipi_for_rfence()) > on_each_cpu(__ipi_flush_tlb_all, NULL, 1); > else > - sbi_remote_sfence_vma(NULL, 0, -1); > + sbi_remote_sfence_vma_asid(NULL, 0, FLUSH_TLB_MAX_SIZE, F= LUSH_TLB_NO_ASID); > } > > struct flush_tlb_range_data { > @@ -69,18 +93,12 @@ static void __ipi_flush_tlb_range_asid(void *info) > local_flush_tlb_range_asid(d->start, d->size, d->stride, d->asid)= ; > } > > -static void __ipi_flush_tlb_range(void *info) > -{ > - struct flush_tlb_range_data *d =3D info; > - > - local_flush_tlb_range(d->start, d->size, d->stride); > -} > - > static void __flush_tlb_range(struct mm_struct *mm, unsigned long start, > unsigned long size, unsigned long stride) > { > struct flush_tlb_range_data ftd; > struct cpumask *cmask =3D mm_cpumask(mm); > + unsigned long asid =3D FLUSH_TLB_NO_ASID; > unsigned int cpuid; > bool broadcast; > > @@ -90,39 +108,24 @@ static void __flush_tlb_range(struct mm_struct *mm, = unsigned long start, > cpuid =3D get_cpu(); > /* check if the tlbflush needs to be sent to other CPUs */ > broadcast =3D cpumask_any_but(cmask, cpuid) < nr_cpu_ids; > - if (static_branch_unlikely(&use_asid_allocator)) { > - unsigned long asid =3D atomic_long_read(&mm->context.id) = & asid_mask; > - > - if (broadcast) { > - if (riscv_use_ipi_for_rfence()) { > - ftd.asid =3D asid; > - ftd.start =3D start; > - ftd.size =3D size; > - ftd.stride =3D stride; > - on_each_cpu_mask(cmask, > - __ipi_flush_tlb_range_as= id, > - &ftd, 1); > - } else > - sbi_remote_sfence_vma_asid(cmask, > - start, size, a= sid); > - } else { > - local_flush_tlb_range_asid(start, size, stride, a= sid); > - } > + > + if (static_branch_unlikely(&use_asid_allocator)) > + asid =3D atomic_long_read(&mm->context.id) & asid_mask; > + > + if (broadcast) { > + if (riscv_use_ipi_for_rfence()) { > + ftd.asid =3D asid; > + ftd.start =3D start; > + ftd.size =3D size; > + ftd.stride =3D stride; > + on_each_cpu_mask(cmask, > + __ipi_flush_tlb_range_asid, > + &ftd, 1); > + } else > + sbi_remote_sfence_vma_asid(cmask, > + start, size, asid); > } else { > - if (broadcast) { > - if (riscv_use_ipi_for_rfence()) { > - ftd.asid =3D 0; > - ftd.start =3D start; > - ftd.size =3D size; > - ftd.stride =3D stride; > - on_each_cpu_mask(cmask, > - __ipi_flush_tlb_range, > - &ftd, 1); > - } else > - sbi_remote_sfence_vma(cmask, start, size)= ; > - } else { > - local_flush_tlb_range(start, size, stride); > - } > + local_flush_tlb_range_asid(start, size, stride, asid); > } > > put_cpu(); > @@ -130,7 +133,7 @@ static void __flush_tlb_range(struct mm_struct *mm, u= nsigned long start, > > void flush_tlb_mm(struct mm_struct *mm) > { > - __flush_tlb_range(mm, 0, -1, PAGE_SIZE); > + __flush_tlb_range(mm, 0, FLUSH_TLB_MAX_SIZE, PAGE_SIZE); > } > > void flush_tlb_mm_range(struct mm_struct *mm, > -- > 2.39.2 >