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Wed, 04 Oct 2023 13:47:58 -0700 (PDT) MIME-Version: 1.0 References: <20230921-th1520-mmc-v1-0-49f76c274fb3@baylibre.com> <20075b03-e3b0-4f29-9ba1-98eed361a44f@sifive.com> <498ffcef-2ff9-495b-8544-b87c5c2eb6e1@arm.com> In-Reply-To: <498ffcef-2ff9-495b-8544-b87c5c2eb6e1@arm.com> From: "Lad, Prabhakar" Date: Wed, 4 Oct 2023 21:47:03 +0100 Message-ID: Subject: Re: [PATCH 0/6] RISC-V: Add eMMC support for TH1520 boards To: Robin Murphy Cc: Samuel Holland , Ulf Hansson , Jisheng Zhang , Drew Fustini , linux-kernel@vger.kernel.org, Linux-MM , Guo Ren , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, Christoph Hellwig , Geert Uytterhoeven , Fabrizio Castro , devicetree@vger.kernel.org, Conor Dooley , Albert Ou , Alexandre Ghiti , Arnd Bergmann , Han Gao , Lad Prabhakar , Jason Kridner , Paul Walmsley , Robert Nelson , linux-mmc@vger.kernel.org, Adrian Hunter , Conor Dooley , =?UTF-8?B?QmrDtnJuIFTDtnBlbA==?= , Rob Herring , Palmer Dabbelt , Xi Ruoyao , Fu Wei Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Rspam-User: X-Stat-Signature: ya8mw3wghei3hzuam4qhdnxiteyg6zc5 X-Rspamd-Server: rspam07 X-Rspamd-Queue-Id: DB24D40016 X-HE-Tag: 1696452480-916500 X-HE-Meta: U2FsdGVkX18Ui5esEmv/3pwQH8r/xgmm4GNKhTtmHLXo8h1j2cLjL7CR11iKMgL45NKSqTzHf8CDChyZQBrcezyqEO+8Lcyqud3+kGy7AM6NH27eC26aEiqxps9l4E/7jTjp42zucquZBafNNTd8A3BrRgpkwCCAPgltN11YXlCtkXRPycTUpojzUDB/4aN9fbAV5Y30XH9y7s91uzJnAmAQ32RIq4fonvsFVEv2WhdXHTVKRn3A8imfsMaEjmSDrLdrJ4/k8aL2ZPiyruEXQt5PCX+bgnjYpERRNCpNi20ROwpd4VEOQAVYSxhLavBy31NE8bUseMkOWqwLHzfV9FcNVZjGnXW5Rfhf9LB4MZfbxzDDhToBQJh12zg2ETVaIQfeVU7gLUC6orJ9LeIg+PLfiy7vqPkRtE4X3zfp2DaZcipuR6IsYGiOazvy24ccPE0fpyDbmG+KtFIB9dWJtzS34Q9Gi8Hoo0E/vZk/Oaaa1mZz/3gG8S35YpUPesiEENMh8m2u5mhxVvrjqtzYedPcB88yMaQ2GU6K9ttbA3WZcZ1TayOQmHTCUTbmzeC477dPB1zoj7HO8hZhKbPbJEvnYhc1QmPJfbVNFhz174et4tJQyDdCVX8f72nSmb9zFSmGqX0mlbyziJq4qnmuERXz3l2WsPte3luzL7iNOi70nYfSaMcda+zmpT+3Yj5Syn0wfkdKdL4GwKSToCqReFHSICLutbP4msZ03eAb1eLo/6dB/9ZSipDNenwZRssMGMkEIVgYYUCL4pP2JwSeXu1Oyrpj4kwDs1PPauAalVaO5OA8cJLl/sWqxa0F9xtfmsY9IL9cIv711CYhECzvY3M3SpStKC3AB9q+mZoB1bUza4qq/U6nYY0IKqbdZvn7YX4f8YwJ6NnNraVAKzpxWUmXCKW1WoOvvwCNT6JIm1ZnRBuZBgrBvqxx/Me01FsZSAcV4yu9INUncUAnohE PiSxIbRn qrV/lGpRx3p6gW9/xpuUhnT4RJW/cwORfghSF4DabyA+nwlvKaiTSYfbwBDvD8koonbhSu/bsM1bLkRyRPSZLlNLrMXbwHFMVmiNdvnXv9dYWsACLgRZuppYv3igdBHBz9N4oqsLXxbsLvspry8XwB0ECayrH9MoT9oRgP8DCRLzZMiweicrbOeY6KEAVRE6Uf+obr6LkYexA5VJzXUMJS2eex3Bf33gysNcX9B46+GIn0jvVAJcwPmWx8hhptqEcP3+dNWoQcexn4XAUKm2ryjPX1ek1eOHa6ISZA17W2dUw3bsOswLxCURD2lBP/pn2n34ipEKOCXp9HoGERVvZ30UKA3un3Ii7p58mQCeC7eErRl3VruhHrwLupi96maXLk/pacycSdJ6x1imhRk7FLZ82V9BvyaJBA6mo2edAfHtvAXX4/lplBwFnqUlt7oPGnlbg8IK5x+HUUiTkqC3pbjYYUETQFvcOVLOCpBfzXXrCIJQyB02X6JA6vWQXvEOHKN3gs4ZyO23BocA= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On Wed, Oct 4, 2023 at 8:38=E2=80=AFPM Robin Murphy = wrote: > > On 2023-10-04 19:49, Samuel Holland wrote: > > On 2023-10-04 12:16 PM, Lad, Prabhakar wrote: > >> On Wed, Oct 4, 2023 at 5:03=E2=80=AFPM Lad, Prabhakar > >> wrote: > >>> > >>> On Wed, Oct 4, 2023 at 3:18=E2=80=AFPM Robin Murphy wrote: > >>>> > >>>> On 04/10/2023 3:02 pm, Icenowy Zheng wrote: > >>>> [...] > >>>>>>>> I believe commit 484861e09f3e ("soc: renesas: Kconfig: Select th= e > >>>>>>>> required configs for RZ/Five SoC") can cause regression on all > >>>>>>>> non-dma-coherent riscv platforms with generic defconfig. This is > >>>>>>>> a common issue. The logic here is: generic riscv defconfig > >>>>>>>> selects > >>>>>>>> ARCH_R9A07G043 which selects DMA_GLOBAL_POOL, which assumes all > >>>>>>>> non-dma-coherent riscv platforms have a dma global pool, this > >>>>>>>> assumption > >>>>>>>> seems not correct. And I believe DMA_GLOBAL_POOL should not be > >>>>>>>> selected by ARCH_SOCFAMILIY, instead, only ARCH under some > >>>>>>>> specific > >>>>>>>> conditions can select it globaly, for example NOMMU ARM and so > >>>>>>>> on. > >>>>>>>> > >>>>>>>> Since this is a regression, what's proper fix? any suggestion is > >>>>>>>> appreciated. > >>>>>> > >>>>>> I think the answer is to not select DMA_GLOBAL_POOL, since that is > >>>>>> only > >>>>> > >>>>> Well I think for RISC-V, it's not NOMMU only but applicable for eve= ry > >>>>> core that does not support Svpbmt or vendor-specific alternatives, > >>>>> because the original RISC-V priv spec does not define memory attrib= utes > >>>>> in page table entries. > >>>>> > >>>>> For the Renesas/Andes case I think a pool is set by OpenSBI with > >>>>> vendor-specific M-mode facility and then passed in DT, and the S-mo= de > >>>>> (which MMU is enabled in) just sees fixed memory attributes, in thi= s > >>>>> case I think DMA_GLOBAL_POOL is needed. > >>>> > >>>> Oh wow, is that really a thing? In that case, either you just can't > >>>> support this platform in a multi-platform kernel, or someone needs t= o do > >>>> some fiddly work in dma-direct to a) introduce the notion of an opti= onal > >>>> global pool, > >>> Looking at the code [0] we do have compile time check for > >>> CONFIG_DMA_GLOBAL_POOL irrespective of this being present in DT or > >>> not, instead if we make it compile time and runtime check ie either > >>> check for DT node or see if pool is available and only then proceed > >>> for allocation form this pool. > >>> > >>> What are your thoughts on this? > >>> > >> Something like the below: > >> > >> diff --git a/include/linux/dma-map-ops.h b/include/linux/dma-map-ops.h > >> index f2fc203fb8a1..7bf41a4634a4 100644 > >> --- a/include/linux/dma-map-ops.h > >> +++ b/include/linux/dma-map-ops.h > >> @@ -198,6 +198,7 @@ int dma_release_from_global_coherent(int order, > >> void *vaddr); > >> int dma_mmap_from_global_coherent(struct vm_area_struct *vma, void *= cpu_addr, > >> size_t size, int *ret); > >> int dma_init_global_coherent(phys_addr_t phys_addr, size_t size); > >> +bool dma_global_pool_available(void); > >> #else > >> static inline void *dma_alloc_from_global_coherent(struct device *de= v, > >> ssize_t size, dma_addr_t *dma_handle) > >> @@ -213,6 +214,10 @@ static inline int > >> dma_mmap_from_global_coherent(struct vm_area_struct *vma, > >> { > >> return 0; > >> } > >> +static inline bool dma_global_pool_available(void) > >> +{ > >> + return false; > >> +} > >> #endif /* CONFIG_DMA_GLOBAL_POOL */ > >> > >> /* > >> diff --git a/kernel/dma/coherent.c b/kernel/dma/coherent.c > >> index c21abc77c53e..605f243b8262 100644 > >> --- a/kernel/dma/coherent.c > >> +++ b/kernel/dma/coherent.c > >> @@ -277,6 +277,14 @@ int dma_mmap_from_dev_coherent(struct device > >> *dev, struct vm_area_struct *vma, > >> #ifdef CONFIG_DMA_GLOBAL_POOL > >> static struct dma_coherent_mem *dma_coherent_default_memory __ro_aft= er_init; > >> > >> +bool dma_global_pool_available(void) > >> +{ > >> + if (!dma_coherent_default_memory) > >> + return false; > >> + > >> + return true; > >> +} > >> + > >> void *dma_alloc_from_global_coherent(struct device *dev, ssize_t siz= e, > >> dma_addr_t *dma_handle) > >> { > >> diff --git a/kernel/dma/direct.c b/kernel/dma/direct.c > >> index 9596ae1aa0da..a599bb731ceb 100644 > >> --- a/kernel/dma/direct.c > >> +++ b/kernel/dma/direct.c > >> @@ -235,7 +235,7 @@ void *dma_direct_alloc(struct device *dev, size_t = size, > >> * If there is a global pool, always allocate from it= for > >> * non-coherent devices. > >> */ > >> - if (IS_ENABLED(CONFIG_DMA_GLOBAL_POOL)) > >> + if (IS_ENABLED(CONFIG_DMA_GLOBAL_POOL) && > >> dma_global_pool_available()) > >> return dma_alloc_from_global_coherent(dev, si= ze, > >> dma_handle); > > > > dma_alloc_from_global_coherent() already checks dma_coherent_default_me= mory, so > > the solution could be even simpler: > > > > --- a/kernel/dma/direct.c > > +++ b/kernel/dma/direct.c > > @@ -232,12 +232,12 @@ void *dma_direct_alloc(struct device *dev, size_t= size, > > attrs); > > > > /* > > - * If there is a global pool, always allocate from it for > > + * If there is a global pool, always try to allocate from= it for > > * non-coherent devices. > > */ > > - if (IS_ENABLED(CONFIG_DMA_GLOBAL_POOL)) > > - return dma_alloc_from_global_coherent(dev, size, > > - dma_handle); > > + ret =3D dma_alloc_from_global_coherent(dev, size, dma_han= dle); > > + if (ret) > > + return ret; > > So if allocation fails because the pool is full, we should go ahead and > remap something that can't work? ;) > > The dma_global_pool_available() idea sort of works, but I'm still > concerned about the case where it *should* have been available but the > platform has been misconfigured, so again we fall through to > If the platform is misconfigured it is bound to fail anyway so should we consider that as a valid case? > DMA_DIRECT_REMAP "successfully" returning a coherent buffer that isn't, > and the user's filesystem gets corrupted. Or at best, they get confused > by weird errors from random devices going wrong. That's why I said it > would be fiddly - the current state of DMA_GLOBAL_POOL as a binary > arch-wide thing is relatively robust and easy to reason about, but > attempting to generalise it further is... less so. > > Thanks, > Robin. > Cheers, Prabhakar