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Wed, 06 Sep 2023 04:49:23 -0700 (PDT) MIME-Version: 1.0 References: <20230801085402.1168351-1-alexghiti@rivosinc.com> <20230801085402.1168351-5-alexghiti@rivosinc.com> In-Reply-To: <20230801085402.1168351-5-alexghiti@rivosinc.com> From: "Lad, Prabhakar" Date: Wed, 6 Sep 2023 12:48:57 +0100 Message-ID: Subject: Re: [PATCH v3 4/4] riscv: Improve flush_tlb_kernel_range() To: Alexandre Ghiti Cc: Geert Uytterhoeven , Will Deacon , "Aneesh Kumar K . V" , Andrew Morton , Nick Piggin , Peter Zijlstra , Mayuresh Chitale , Vincent Chen , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-arch@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Andrew Jones Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Rspamd-Queue-Id: 69C5F1C0010 X-Rspam-User: X-Rspamd-Server: rspam02 X-Stat-Signature: kak9korreq1hxd5496n1f9yawopngbn9 X-HE-Tag: 1694000964-830818 X-HE-Meta: U2FsdGVkX19hRsr8gRvhAW+CP4ylc/RAtaYoC6PBlG06gYtBIFfqrrMMB7w4y/YqCZw41RXtimbp4ETHgYzUqnezEdHbslKpWzk49h+qFaloGEP1/WCXaJmK0O/DZZnvEl/bXulHhiNBJfWaR2rQxiDrEhJVgHmnr34roEYqYYX0wivdL+5HNanhoRudydQypIVEVPqr8tI0h6Akli96AhVVCGJ0KAiVrmgTN2wcUiCOWT/Tdnao2eIhSr7Aw33y3q2jOPsOX9Dq7AbePxvDOchcyrZk47pXKR4vqqWdLU6sCDHuCXD6i9SeP0lUaGXcwFeW753X58qUyYTQ8tr1bhaefYRHg6LJFykrwScKDIFkyBqPq5pSB8V7IdcMdFYBi/m3BtxBrVJ2SVXTneGmtvMm0rlBzZ/4WWmgtOC3pY/6K9E6BwlgRtfbCl6RRk7HNeRXwBNqIWIMZ6Vf2FtbFmiHKqOgIHTii0mRpx4bJ7757IGBjvfTTEmDiQ5d1CuwK0v6EaUyjJeJlDYYGW6ifCJltsqsLGEzYsNgNHVJBKji2elBrdWhVgJN7Ylti90rrUhB9NilcD0E7nGmbZ6pXFx2OkVHJHI7lmPr10htHPla2JnnwhhZCPeo/aRZlKkgT5yEI96emIRHvaE0In+9wvH9eWNQ9sMgan9m4x53TjlumTLqARQZLQHMFzSv9Px0aWSRSBjQEBk2oZcXG17Lg6PUWOeLo7Ky+HaA7OmTrf2lrFDamkj3vF7n/NXd8vO9zyOpLO7jXrbJyIQURIXYLcaOY8qOOU4vRkeNHCz7GCEcG8CqMAqiylpqEjM/U72rE24AFfNiBOorexZrBaFWCrlalc6ic7Zj7P/ujTaX0g/SjkAEHkDNQ73iHv3sk8h6TP4O95qIfdVf+J1Q3TLnUW9Y8jXpA0yoOWblPtgfYBzgJmkeEGtezT1Ul93IJuTUg+/wixHENl6Qp3U0/Da LNeD3sZV pQoHRfxYc3Z4O/s2TSSywiXx63RKRhQAhcrJEtu8KPQbKOL2EmR8tRJlRGqHtVq9wnNfcyFts4LIa3ATHJuSV1V1UD67baxjPIG56YZTux9Q86/NUIBF1ARonTjaGrASXyZX4nfzEoskytmw7qu8+j3H4Eqzda+15Y58Yjnidgbp+mamz6XwACf3vI1eeAVhjjrlKILc4r6PXs7O1y8gtyWihJjZ1JuUhmGf/DwsHDCT1QmGbOuhHqT9owwjFQb1N0fOxaPFG1Zysch+gjibVF+0tTWPm/7/FYBhpCEMwixoVKmM9OAeCU9HnOL6GZVkvX6cuzULz/5DqKjw/3281xlI5tTD0F83J2g7+4Ko5seqXs1jiconQQGHF+soTFdlVPXUud/erOfWey+07cMQIqmfs3wGCKtulOaid/UdGya3t9lP2kakIjVZkmGtqkJ7Q18caQ8CADWkaF4LoXwGgmvgoqMvoEmZ6MPtwwe3AfLgIVpog+nLV1IbDgV3dc4ayD7LZ2a+LujruYW4lmfIz9VGZ/NNVt4F3Q3jSOJLmwmt8+5QDQIn40ZNEYCv3VPPR7eWItIX9ZHPIEOwllGXh6nbh/nJ5NIqxJC/yHfC56HWGt+Ug/yhA/c3g7qe0gDhu+MCjAuiQZMnJNHP6SJqcrRp/xw== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Hi Alexandre, On Tue, Aug 1, 2023 at 9:58=E2=80=AFAM Alexandre Ghiti wrote: > > This function used to simply flush the whole tlb of all harts, be more > subtile and try to only flush the range. > > The problem is that we can only use PAGE_SIZE as stride since we don't kn= ow > the size of the underlying mapping and then this function will be improve= d > only if the size of the region to flush is < threshold * PAGE_SIZE. > > Signed-off-by: Alexandre Ghiti > Reviewed-by: Andrew Jones > --- > arch/riscv/include/asm/tlbflush.h | 11 +++++----- > arch/riscv/mm/tlbflush.c | 34 +++++++++++++++++++++++-------- > 2 files changed, 31 insertions(+), 14 deletions(-) > After applying this patch, I am seeing module load issues on RZ/Five (complete log [0]). I am testing defconfig + [1] (rz/five related configs). Any pointers on what could be an issue here? [0] https://paste.debian.net/1291116/ [1] https://paste.debian.net/1291118/ Cheers, Prabhakar > diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/t= lbflush.h > index f5c4fb0ae642..7426fdcd8ec5 100644 > --- a/arch/riscv/include/asm/tlbflush.h > +++ b/arch/riscv/include/asm/tlbflush.h > @@ -37,6 +37,7 @@ void flush_tlb_mm_range(struct mm_struct *mm, unsigned = long start, > void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr); > void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, > unsigned long end); > +void flush_tlb_kernel_range(unsigned long start, unsigned long end); > #ifdef CONFIG_TRANSPARENT_HUGEPAGE > #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE > void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start= , > @@ -53,15 +54,15 @@ static inline void flush_tlb_range(struct vm_area_str= uct *vma, > local_flush_tlb_all(); > } > > -#define flush_tlb_mm(mm) flush_tlb_all() > -#define flush_tlb_mm_range(mm, start, end, page_size) flush_tlb_all() > -#endif /* !CONFIG_SMP || !CONFIG_MMU */ > - > /* Flush a range of kernel pages */ > static inline void flush_tlb_kernel_range(unsigned long start, > unsigned long end) > { > - flush_tlb_all(); > + local_flush_tlb_all(); > } > > +#define flush_tlb_mm(mm) flush_tlb_all() > +#define flush_tlb_mm_range(mm, start, end, page_size) flush_tlb_all() > +#endif /* !CONFIG_SMP || !CONFIG_MMU */ > + > #endif /* _ASM_RISCV_TLBFLUSH_H */ > diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c > index 0c955c474f3a..687808013758 100644 > --- a/arch/riscv/mm/tlbflush.c > +++ b/arch/riscv/mm/tlbflush.c > @@ -120,18 +120,27 @@ static void __flush_tlb_range(struct mm_struct *mm,= unsigned long start, > unsigned long size, unsigned long stride) > { > struct flush_tlb_range_data ftd; > - struct cpumask *cmask =3D mm_cpumask(mm); > - unsigned int cpuid; > + struct cpumask *cmask, full_cmask; > bool broadcast; > > - if (cpumask_empty(cmask)) > - return; > + if (mm) { > + unsigned int cpuid; > + > + cmask =3D mm_cpumask(mm); > + if (cpumask_empty(cmask)) > + return; > + > + cpuid =3D get_cpu(); > + /* check if the tlbflush needs to be sent to other CPUs *= / > + broadcast =3D cpumask_any_but(cmask, cpuid) < nr_cpu_ids; > + } else { > + cpumask_setall(&full_cmask); > + cmask =3D &full_cmask; > + broadcast =3D true; > + } > > - cpuid =3D get_cpu(); > - /* check if the tlbflush needs to be sent to other CPUs */ > - broadcast =3D cpumask_any_but(cmask, cpuid) < nr_cpu_ids; > if (static_branch_unlikely(&use_asid_allocator)) { > - unsigned long asid =3D atomic_long_read(&mm->context.id) = & asid_mask; > + unsigned long asid =3D mm ? atomic_long_read(&mm->context= .id) & asid_mask : 0; > > if (broadcast) { > if (riscv_use_ipi_for_rfence()) { > @@ -165,7 +174,8 @@ static void __flush_tlb_range(struct mm_struct *mm, u= nsigned long start, > } > } > > - put_cpu(); > + if (mm) > + put_cpu(); > } > > void flush_tlb_mm(struct mm_struct *mm) > @@ -196,6 +206,12 @@ void flush_tlb_range(struct vm_area_struct *vma, uns= igned long start, > > __flush_tlb_range(vma->vm_mm, start, end - start, stride_size); > } > + > +void flush_tlb_kernel_range(unsigned long start, unsigned long end) > +{ > + __flush_tlb_range(NULL, start, end, PAGE_SIZE); > +} > + > #ifdef CONFIG_TRANSPARENT_HUGEPAGE > void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start= , > unsigned long end) > -- > 2.39.2 > >