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From: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
To: Alexandre Ghiti <alexghiti@rivosinc.com>
Cc: Will Deacon <will@kernel.org>,
	"Aneesh Kumar K . V" <aneesh.kumar@linux.ibm.com>,
	 Andrew Morton <akpm@linux-foundation.org>,
	Nick Piggin <npiggin@gmail.com>,
	 Peter Zijlstra <peterz@infradead.org>,
	Mayuresh Chitale <mchitale@ventanamicro.com>,
	 Vincent Chen <vincent.chen@sifive.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	 Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	linux-arch@vger.kernel.org,  linux-mm@kvack.org,
	linux-riscv@lists.infradead.org,  linux-kernel@vger.kernel.org,
	Samuel Holland <samuel@sholland.org>,
	 Andrew Jones <ajones@ventanamicro.com>
Subject: Re: [PATCH v4 2/4] riscv: Improve flush_tlb_range() for hugetlb pages
Date: Tue, 19 Sep 2023 13:07:51 +0100	[thread overview]
Message-ID: <CA+V-a8soezvPad=m4m2CN5QJ5qVOAxyjA6z=w3fUu7h8EF_B-Q@mail.gmail.com> (raw)
In-Reply-To: <20230911131224.61924-3-alexghiti@rivosinc.com>

On Mon, Sep 11, 2023 at 2:14 PM Alexandre Ghiti <alexghiti@rivosinc.com> wrote:
>
> flush_tlb_range() uses a fixed stride of PAGE_SIZE and in its current form,
> when a hugetlb mapping needs to be flushed, flush_tlb_range() flushes the
> whole tlb: so set a stride of the size of the hugetlb mapping in order to
> only flush the hugetlb mapping. However, if the hugepage is a NAPOT region,
> all PTEs that constitute this mapping must be invalidated, so the stride
> size must actually be the size of the PTE.
>
> Note that THPs are directly handled by flush_pmd_tlb_range().
>
> Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> ---
>  arch/riscv/mm/tlbflush.c | 39 ++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 38 insertions(+), 1 deletion(-)
>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> #
On RZ/Five SMARC

Cheers,
Prabhakar

> diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c
> index fa03289853d8..5bda6d4fed90 100644
> --- a/arch/riscv/mm/tlbflush.c
> +++ b/arch/riscv/mm/tlbflush.c
> @@ -3,6 +3,7 @@
>  #include <linux/mm.h>
>  #include <linux/smp.h>
>  #include <linux/sched.h>
> +#include <linux/hugetlb.h>
>  #include <asm/sbi.h>
>  #include <asm/mmu_context.h>
>
> @@ -147,7 +148,43 @@ void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
>  void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
>                      unsigned long end)
>  {
> -       __flush_tlb_range(vma->vm_mm, start, end - start, PAGE_SIZE);
> +       unsigned long stride_size;
> +
> +       stride_size = is_vm_hugetlb_page(vma) ?
> +                               huge_page_size(hstate_vma(vma)) :
> +                               PAGE_SIZE;
> +
> +#ifdef CONFIG_RISCV_ISA_SVNAPOT
> +       /*
> +        * As stated in the privileged specification, every PTE in a NAPOT
> +        * region must be invalidated, so reset the stride in that case.
> +        */
> +       if (has_svnapot()) {
> +               unsigned long order, napot_size;
> +
> +               for_each_napot_order(order) {
> +                       napot_size = napot_cont_size(order);
> +
> +                       if (stride_size != napot_size)
> +                               continue;
> +
> +                       if (napot_size >= PGDIR_SIZE)
> +                               stride_size = PGDIR_SIZE;
> +                       else if (napot_size >= P4D_SIZE)
> +                               stride_size = P4D_SIZE;
> +                       else if (napot_size >= PUD_SIZE)
> +                               stride_size = PUD_SIZE;
> +                       else if (napot_size >= PMD_SIZE)
> +                               stride_size = PMD_SIZE;
> +                       else
> +                               stride_size = PAGE_SIZE;
> +
> +                       break;
> +               }
> +       }
> +#endif
> +
> +       __flush_tlb_range(vma->vm_mm, start, end - start, stride_size);
>  }
>  #ifdef CONFIG_TRANSPARENT_HUGEPAGE
>  void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start,
> --
> 2.39.2
>


  reply	other threads:[~2023-09-19 12:08 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-11 13:12 [PATCH v4 0/4] riscv: tlb flush improvements Alexandre Ghiti
2023-09-11 13:12 ` [PATCH v4 1/4] riscv: Improve flush_tlb() Alexandre Ghiti
2023-09-19 12:07   ` Lad, Prabhakar
2023-10-09 17:53   ` Samuel Holland
2023-10-18 11:26     ` Alexandre Ghiti
2023-09-11 13:12 ` [PATCH v4 2/4] riscv: Improve flush_tlb_range() for hugetlb pages Alexandre Ghiti
2023-09-19 12:07   ` Lad, Prabhakar [this message]
2023-10-09 17:53   ` Samuel Holland
2023-10-18 11:32     ` Alexandre Ghiti
2023-09-11 13:12 ` [PATCH v4 3/4] riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlb Alexandre Ghiti
2023-09-19 12:09   ` Lad, Prabhakar
2023-09-11 13:12 ` [PATCH v4 4/4] riscv: Improve flush_tlb_kernel_range() Alexandre Ghiti
2023-09-13  8:04   ` Alexandre Ghiti
2023-09-13  8:23     ` Lad, Prabhakar
2023-09-13  8:32       ` Alexandre Ghiti
2023-09-19 12:09   ` Lad, Prabhakar

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