* [linux-next:master 13230/13643] arch/riscv/errata/andes/errata.c:29:23: error: storage size of 'ret' isn't known
@ 2023-08-31 8:52 kernel test robot
2023-08-31 9:16 ` [WARNING: ATTACHMENT UNSCANNED]Re: " Conor Dooley
0 siblings, 1 reply; 11+ messages in thread
From: kernel test robot @ 2023-08-31 8:52 UTC (permalink / raw)
To: Lad Prabhakar
Cc: oe-kbuild-all, Linux Memory Management List, Palmer Dabbelt,
Conor Dooley
tree: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
head: a47fc304d2b678db1a5d760a7d644dac9b067752
commit: f2863f30d1b05e5ecf61c063609cb974954d47f8 [13230/13643] riscv: errata: Add Andes alternative ports
config: riscv-randconfig-001-20230831 (https://download.01.org/0day-ci/archive/20230831/202308311610.ec6bm2G8-lkp@intel.com/config)
compiler: riscv64-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20230831/202308311610.ec6bm2G8-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202308311610.ec6bm2G8-lkp@intel.com/
All error/warnings (new ones prefixed by >>):
arch/riscv/errata/andes/errata.c: In function 'ax45mp_iocp_sw_workaround':
>> arch/riscv/errata/andes/errata.c:29:23: error: storage size of 'ret' isn't known
29 | struct sbiret ret;
| ^~~
>> arch/riscv/errata/andes/errata.c:35:15: error: implicit declaration of function 'sbi_ecall' [-Werror=implicit-function-declaration]
35 | ret = sbi_ecall(ANDESTECH_SBI_EXT_ANDES, ANDES_SBI_EXT_IOCP_SW_WORKAROUND,
| ^~~~~~~~~
>> arch/riscv/errata/andes/errata.c:29:23: warning: unused variable 'ret' [-Wunused-variable]
29 | struct sbiret ret;
| ^~~
cc1: some warnings being treated as errors
vim +29 arch/riscv/errata/andes/errata.c
26
27 static long ax45mp_iocp_sw_workaround(void)
28 {
> 29 struct sbiret ret;
30
31 /*
32 * ANDES_SBI_EXT_IOCP_SW_WORKAROUND SBI EXT checks if the IOCP is missing and
33 * cache is controllable only then CMO will be applied to the platform.
34 */
> 35 ret = sbi_ecall(ANDESTECH_SBI_EXT_ANDES, ANDES_SBI_EXT_IOCP_SW_WORKAROUND,
36 0, 0, 0, 0, 0, 0);
37
38 return ret.error ? 0 : ret.value;
39 }
40
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 11+ messages in thread
* [WARNING: ATTACHMENT UNSCANNED]Re: [linux-next:master 13230/13643] arch/riscv/errata/andes/errata.c:29:23: error: storage size of 'ret' isn't known
2023-08-31 8:52 [linux-next:master 13230/13643] arch/riscv/errata/andes/errata.c:29:23: error: storage size of 'ret' isn't known kernel test robot
@ 2023-08-31 9:16 ` Conor Dooley
2023-08-31 11:22 ` Lad, Prabhakar
0 siblings, 1 reply; 11+ messages in thread
From: Conor Dooley @ 2023-08-31 9:16 UTC (permalink / raw)
To: kernel test robot
Cc: Lad Prabhakar, oe-kbuild-all, Linux Memory Management List,
Palmer Dabbelt
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On Thu, Aug 31, 2023 at 04:52:00PM +0800, kernel test robot wrote:
> tree: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
> head: a47fc304d2b678db1a5d760a7d644dac9b067752
> commit: f2863f30d1b05e5ecf61c063609cb974954d47f8 [13230/13643] riscv: errata: Add Andes alternative ports
> config: riscv-randconfig-001-20230831 (https://download.01.org/0day-ci/archive/20230831/202308311610.ec6bm2G8-lkp@intel.com/config)
> compiler: riscv64-linux-gcc (GCC) 13.2.0
> reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20230831/202308311610.ec6bm2G8-lkp@intel.com/reproduce)
>
> If you fix the issue in a separate patch/commit (i.e. not just a new version of
> the same patch/commit), kindly add following tags
> | Reported-by: kernel test robot <lkp@intel.com>
> | Closes: https://lore.kernel.org/oe-kbuild-all/202308311610.ec6bm2G8-lkp@intel.com/
>
> All error/warnings (new ones prefixed by >>):
>
> arch/riscv/errata/andes/errata.c: In function 'ax45mp_iocp_sw_workaround':
> >> arch/riscv/errata/andes/errata.c:29:23: error: storage size of 'ret' isn't known
> 29 | struct sbiret ret;
> | ^~~
> >> arch/riscv/errata/andes/errata.c:35:15: error: implicit declaration of function 'sbi_ecall' [-Werror=implicit-function-declaration]
> 35 | ret = sbi_ecall(ANDESTECH_SBI_EXT_ANDES, ANDES_SBI_EXT_IOCP_SW_WORKAROUND,
> | ^~~~~~~~~
> >> arch/riscv/errata/andes/errata.c:29:23: warning: unused variable 'ret' [-Wunused-variable]
> 29 | struct sbiret ret;
> | ^~~
> cc1: some warnings being treated as errors
>
>
> vim +29 arch/riscv/errata/andes/errata.c
>
> 26
> 27 static long ax45mp_iocp_sw_workaround(void)
> 28 {
> > 29 struct sbiret ret;
> 30
> 31 /*
> 32 * ANDES_SBI_EXT_IOCP_SW_WORKAROUND SBI EXT checks if the IOCP is missing and
> 33 * cache is controllable only then CMO will be applied to the platform.
> 34 */
> > 35 ret = sbi_ecall(ANDESTECH_SBI_EXT_ANDES, ANDES_SBI_EXT_IOCP_SW_WORKAROUND,
> 36 0, 0, 0, 0, 0, 0);
> 37
> 38 return ret.error ? 0 : ret.value;
> 39 }
> 40
Looks like the config doesn't enable SBI, so ERRATA_ANDES_CMO will need
to grow a dependency on RISCV_SBI.
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [WARNING: ATTACHMENT UNSCANNED]Re: [linux-next:master 13230/13643] arch/riscv/errata/andes/errata.c:29:23: error: storage size of 'ret' isn't known
2023-08-31 9:16 ` [WARNING: ATTACHMENT UNSCANNED]Re: " Conor Dooley
@ 2023-08-31 11:22 ` Lad, Prabhakar
2023-08-31 11:33 ` Conor Dooley
0 siblings, 1 reply; 11+ messages in thread
From: Lad, Prabhakar @ 2023-08-31 11:22 UTC (permalink / raw)
To: Conor Dooley
Cc: Geert Uytterhoeven, kernel test robot, Lad Prabhakar,
oe-kbuild-all, Linux Memory Management List, Palmer Dabbelt
Hi Conor,
On Thu, Aug 31, 2023 at 10:44 AM Conor Dooley
<conor.dooley@microchip.com> wrote:
>
> On Thu, Aug 31, 2023 at 04:52:00PM +0800, kernel test robot wrote:
> > tree: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
> > head: a47fc304d2b678db1a5d760a7d644dac9b067752
> > commit: f2863f30d1b05e5ecf61c063609cb974954d47f8 [13230/13643] riscv: errata: Add Andes alternative ports
> > config: riscv-randconfig-001-20230831 (https://download.01.org/0day-ci/archive/20230831/202308311610.ec6bm2G8-lkp@intel.com/config)
> > compiler: riscv64-linux-gcc (GCC) 13.2.0
> > reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20230831/202308311610.ec6bm2G8-lkp@intel.com/reproduce)
> >
> > If you fix the issue in a separate patch/commit (i.e. not just a new version of
> > the same patch/commit), kindly add following tags
> > | Reported-by: kernel test robot <lkp@intel.com>
> > | Closes: https://lore.kernel.org/oe-kbuild-all/202308311610.ec6bm2G8-lkp@intel.com/
> >
> > All error/warnings (new ones prefixed by >>):
> >
> > arch/riscv/errata/andes/errata.c: In function 'ax45mp_iocp_sw_workaround':
> > >> arch/riscv/errata/andes/errata.c:29:23: error: storage size of 'ret' isn't known
> > 29 | struct sbiret ret;
> > | ^~~
> > >> arch/riscv/errata/andes/errata.c:35:15: error: implicit declaration of function 'sbi_ecall' [-Werror=implicit-function-declaration]
> > 35 | ret = sbi_ecall(ANDESTECH_SBI_EXT_ANDES, ANDES_SBI_EXT_IOCP_SW_WORKAROUND,
> > | ^~~~~~~~~
> > >> arch/riscv/errata/andes/errata.c:29:23: warning: unused variable 'ret' [-Wunused-variable]
> > 29 | struct sbiret ret;
> > | ^~~
> > cc1: some warnings being treated as errors
> >
> >
> > vim +29 arch/riscv/errata/andes/errata.c
> >
> > 26
> > 27 static long ax45mp_iocp_sw_workaround(void)
> > 28 {
> > > 29 struct sbiret ret;
> > 30
> > 31 /*
> > 32 * ANDES_SBI_EXT_IOCP_SW_WORKAROUND SBI EXT checks if the IOCP is missing and
> > 33 * cache is controllable only then CMO will be applied to the platform.
> > 34 */
> > > 35 ret = sbi_ecall(ANDESTECH_SBI_EXT_ANDES, ANDES_SBI_EXT_IOCP_SW_WORKAROUND,
> > 36 0, 0, 0, 0, 0, 0);
> > 37
> > 38 return ret.error ? 0 : ret.value;
> > 39 }
> > 40
>
> Looks like the config doesn't enable SBI, so ERRATA_ANDES_CMO will need
> to grow a dependency on RISCV_SBI.
I think adding dependency for RISCV_SBI on ERRATA_ANDES would be a good idea.
While at it I am seeing below warnings with this randconfig:
WARNING: unmet direct dependencies detected for ERRATA_ANDES_CMO
Depends on [n]: ERRATA_ANDES [=y] && MMU [=n] && ARCH_R9A07G043 [=y]
Selected by [y]:
- ARCH_R9A07G043 [=y] && SOC_RENESAS [=y] && RISCV [=y]
WARNING: unmet direct dependencies detected for AX45MP_L2_CACHE
Depends on [n]: RISCV_DMA_NONCOHERENT [=n]
Selected by [y]:
- ARCH_R9A07G043 [=y] && SOC_RENESAS [=y] && RISCV [=y]
configuration written to .config
*** End of the configuration.
*** Execute 'make' to start the build or try 'make help'.
For which I will send the below fix:
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -334,10 +334,10 @@ if RISCV
config ARCH_R9A07G043
bool "RISC-V Platform support for RZ/Five"
select ARCH_RZG2L
- select AX45MP_L2_CACHE
+ imply AX45MP_L2_CACHE
select DMA_GLOBAL_POOL
- select ERRATA_ANDES
- select ERRATA_ANDES_CMO
+ imply ERRATA_ANDES
+ imply ERRATA_ANDES_CMO
help
This enables support for the Renesas RZ/Five SoC.
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [WARNING: ATTACHMENT UNSCANNED]Re: [linux-next:master 13230/13643] arch/riscv/errata/andes/errata.c:29:23: error: storage size of 'ret' isn't known
2023-08-31 11:22 ` Lad, Prabhakar
@ 2023-08-31 11:33 ` Conor Dooley
2023-08-31 11:53 ` Lad, Prabhakar
0 siblings, 1 reply; 11+ messages in thread
From: Conor Dooley @ 2023-08-31 11:33 UTC (permalink / raw)
To: Lad, Prabhakar
Cc: Geert Uytterhoeven, kernel test robot, Lad Prabhakar,
oe-kbuild-all, Linux Memory Management List, Palmer Dabbelt
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On Thu, Aug 31, 2023 at 12:22:50PM +0100, Lad, Prabhakar wrote:
> Hi Conor,
>
> On Thu, Aug 31, 2023 at 10:44 AM Conor Dooley
> <conor.dooley@microchip.com> wrote:
> >
> > On Thu, Aug 31, 2023 at 04:52:00PM +0800, kernel test robot wrote:
> > > tree: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
> > > head: a47fc304d2b678db1a5d760a7d644dac9b067752
> > > commit: f2863f30d1b05e5ecf61c063609cb974954d47f8 [13230/13643] riscv: errata: Add Andes alternative ports
> > > config: riscv-randconfig-001-20230831 (https://download.01.org/0day-ci/archive/20230831/202308311610.ec6bm2G8-lkp@intel.com/config)
> > > compiler: riscv64-linux-gcc (GCC) 13.2.0
> > > reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20230831/202308311610.ec6bm2G8-lkp@intel.com/reproduce)
> > >
> > > If you fix the issue in a separate patch/commit (i.e. not just a new version of
> > > the same patch/commit), kindly add following tags
> > > | Reported-by: kernel test robot <lkp@intel.com>
> > > | Closes: https://lore.kernel.org/oe-kbuild-all/202308311610.ec6bm2G8-lkp@intel.com/
> > >
> > > All error/warnings (new ones prefixed by >>):
> > >
> > > arch/riscv/errata/andes/errata.c: In function 'ax45mp_iocp_sw_workaround':
> > > >> arch/riscv/errata/andes/errata.c:29:23: error: storage size of 'ret' isn't known
> > > 29 | struct sbiret ret;
> > > | ^~~
> > > >> arch/riscv/errata/andes/errata.c:35:15: error: implicit declaration of function 'sbi_ecall' [-Werror=implicit-function-declaration]
> > > 35 | ret = sbi_ecall(ANDESTECH_SBI_EXT_ANDES, ANDES_SBI_EXT_IOCP_SW_WORKAROUND,
> > > | ^~~~~~~~~
> > > >> arch/riscv/errata/andes/errata.c:29:23: warning: unused variable 'ret' [-Wunused-variable]
> > > 29 | struct sbiret ret;
> > > | ^~~
> > > cc1: some warnings being treated as errors
> > >
> > >
> > > vim +29 arch/riscv/errata/andes/errata.c
> > >
> > > 26
> > > 27 static long ax45mp_iocp_sw_workaround(void)
> > > 28 {
> > > > 29 struct sbiret ret;
> > > 30
> > > 31 /*
> > > 32 * ANDES_SBI_EXT_IOCP_SW_WORKAROUND SBI EXT checks if the IOCP is missing and
> > > 33 * cache is controllable only then CMO will be applied to the platform.
> > > 34 */
> > > > 35 ret = sbi_ecall(ANDESTECH_SBI_EXT_ANDES, ANDES_SBI_EXT_IOCP_SW_WORKAROUND,
> > > 36 0, 0, 0, 0, 0, 0);
> > > 37
> > > 38 return ret.error ? 0 : ret.value;
> > > 39 }
> > > 40
> >
> > Looks like the config doesn't enable SBI, so ERRATA_ANDES_CMO will need
> > to grow a dependency on RISCV_SBI.
> I think adding dependency for RISCV_SBI on ERRATA_ANDES would be a good idea.
>
> While at it I am seeing below warnings with this randconfig:
> WARNING: unmet direct dependencies detected for ERRATA_ANDES_CMO
> Depends on [n]: ERRATA_ANDES [=y] && MMU [=n] && ARCH_R9A07G043 [=y]
> Selected by [y]:
> - ARCH_R9A07G043 [=y] && SOC_RENESAS [=y] && RISCV [=y]
>
> WARNING: unmet direct dependencies detected for AX45MP_L2_CACHE
> Depends on [n]: RISCV_DMA_NONCOHERENT [=n]
> Selected by [y]:
> - ARCH_R9A07G043 [=y] && SOC_RENESAS [=y] && RISCV [=y]
> configuration written to .config
>
> *** End of the configuration.
> *** Execute 'make' to start the build or try 'make help'.
>
> For which I will send the below fix:
> --- a/drivers/soc/renesas/Kconfig
> +++ b/drivers/soc/renesas/Kconfig
> @@ -334,10 +334,10 @@ if RISCV
> config ARCH_R9A07G043
> bool "RISC-V Platform support for RZ/Five"
> select ARCH_RZG2L
> - select AX45MP_L2_CACHE
> + imply AX45MP_L2_CACHE
> select DMA_GLOBAL_POOL
> - select ERRATA_ANDES
> - select ERRATA_ANDES_CMO
> + imply ERRATA_ANDES
> + imply ERRATA_ANDES_CMO
> help
> This enables support for the Renesas RZ/Five SoC.
I've only ever heard bad things from Arnd about using imply.
Why don't you just make the erratum config option select
RISCV_DMA_NONCOHERENT, just like the THEAD_CMO erratum does?
The cache driver should probably then depend on the erratum Kconfig
option, since there's no point in having it otherwise?
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [WARNING: ATTACHMENT UNSCANNED]Re: [linux-next:master 13230/13643] arch/riscv/errata/andes/errata.c:29:23: error: storage size of 'ret' isn't known
2023-08-31 11:33 ` Conor Dooley
@ 2023-08-31 11:53 ` Lad, Prabhakar
2023-08-31 12:01 ` Geert Uytterhoeven
0 siblings, 1 reply; 11+ messages in thread
From: Lad, Prabhakar @ 2023-08-31 11:53 UTC (permalink / raw)
To: Conor Dooley, Geert Uytterhoeven
Cc: kernel test robot, Lad Prabhakar, oe-kbuild-all,
Linux Memory Management List, Palmer Dabbelt
Hi Conor,
On Thu, Aug 31, 2023 at 12:34 PM Conor Dooley
<conor.dooley@microchip.com> wrote:
>
> On Thu, Aug 31, 2023 at 12:22:50PM +0100, Lad, Prabhakar wrote:
> > Hi Conor,
> >
> > On Thu, Aug 31, 2023 at 10:44 AM Conor Dooley
> > <conor.dooley@microchip.com> wrote:
> > >
> > > On Thu, Aug 31, 2023 at 04:52:00PM +0800, kernel test robot wrote:
> > > > tree: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
> > > > head: a47fc304d2b678db1a5d760a7d644dac9b067752
> > > > commit: f2863f30d1b05e5ecf61c063609cb974954d47f8 [13230/13643] riscv: errata: Add Andes alternative ports
> > > > config: riscv-randconfig-001-20230831 (https://download.01.org/0day-ci/archive/20230831/202308311610.ec6bm2G8-lkp@intel.com/config)
> > > > compiler: riscv64-linux-gcc (GCC) 13.2.0
> > > > reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20230831/202308311610.ec6bm2G8-lkp@intel.com/reproduce)
> > > >
> > > > If you fix the issue in a separate patch/commit (i.e. not just a new version of
> > > > the same patch/commit), kindly add following tags
> > > > | Reported-by: kernel test robot <lkp@intel.com>
> > > > | Closes: https://lore.kernel.org/oe-kbuild-all/202308311610.ec6bm2G8-lkp@intel.com/
> > > >
> > > > All error/warnings (new ones prefixed by >>):
> > > >
> > > > arch/riscv/errata/andes/errata.c: In function 'ax45mp_iocp_sw_workaround':
> > > > >> arch/riscv/errata/andes/errata.c:29:23: error: storage size of 'ret' isn't known
> > > > 29 | struct sbiret ret;
> > > > | ^~~
> > > > >> arch/riscv/errata/andes/errata.c:35:15: error: implicit declaration of function 'sbi_ecall' [-Werror=implicit-function-declaration]
> > > > 35 | ret = sbi_ecall(ANDESTECH_SBI_EXT_ANDES, ANDES_SBI_EXT_IOCP_SW_WORKAROUND,
> > > > | ^~~~~~~~~
> > > > >> arch/riscv/errata/andes/errata.c:29:23: warning: unused variable 'ret' [-Wunused-variable]
> > > > 29 | struct sbiret ret;
> > > > | ^~~
> > > > cc1: some warnings being treated as errors
> > > >
> > > >
> > > > vim +29 arch/riscv/errata/andes/errata.c
> > > >
> > > > 26
> > > > 27 static long ax45mp_iocp_sw_workaround(void)
> > > > 28 {
> > > > > 29 struct sbiret ret;
> > > > 30
> > > > 31 /*
> > > > 32 * ANDES_SBI_EXT_IOCP_SW_WORKAROUND SBI EXT checks if the IOCP is missing and
> > > > 33 * cache is controllable only then CMO will be applied to the platform.
> > > > 34 */
> > > > > 35 ret = sbi_ecall(ANDESTECH_SBI_EXT_ANDES, ANDES_SBI_EXT_IOCP_SW_WORKAROUND,
> > > > 36 0, 0, 0, 0, 0, 0);
> > > > 37
> > > > 38 return ret.error ? 0 : ret.value;
> > > > 39 }
> > > > 40
> > >
> > > Looks like the config doesn't enable SBI, so ERRATA_ANDES_CMO will need
> > > to grow a dependency on RISCV_SBI.
> > I think adding dependency for RISCV_SBI on ERRATA_ANDES would be a good idea.
> >
> > While at it I am seeing below warnings with this randconfig:
> > WARNING: unmet direct dependencies detected for ERRATA_ANDES_CMO
> > Depends on [n]: ERRATA_ANDES [=y] && MMU [=n] && ARCH_R9A07G043 [=y]
> > Selected by [y]:
> > - ARCH_R9A07G043 [=y] && SOC_RENESAS [=y] && RISCV [=y]
> >
> > WARNING: unmet direct dependencies detected for AX45MP_L2_CACHE
> > Depends on [n]: RISCV_DMA_NONCOHERENT [=n]
> > Selected by [y]:
> > - ARCH_R9A07G043 [=y] && SOC_RENESAS [=y] && RISCV [=y]
> > configuration written to .config
> >
> > *** End of the configuration.
> > *** Execute 'make' to start the build or try 'make help'.
> >
> > For which I will send the below fix:
> > --- a/drivers/soc/renesas/Kconfig
> > +++ b/drivers/soc/renesas/Kconfig
> > @@ -334,10 +334,10 @@ if RISCV
> > config ARCH_R9A07G043
> > bool "RISC-V Platform support for RZ/Five"
> > select ARCH_RZG2L
> > - select AX45MP_L2_CACHE
> > + imply AX45MP_L2_CACHE
> > select DMA_GLOBAL_POOL
> > - select ERRATA_ANDES
> > - select ERRATA_ANDES_CMO
> > + imply ERRATA_ANDES
> > + imply ERRATA_ANDES_CMO
> > help
> > This enables support for the Renesas RZ/Five SoC.
>
> I've only ever heard bad things from Arnd about using imply.
>
> Why don't you just make the erratum config option select
> RISCV_DMA_NONCOHERENT, just like the THEAD_CMO erratum does?
> The cache driver should probably then depend on the erratum Kconfig
> option, since there's no point in having it otherwise?
>
Agreed.
I have the below proposal:
---------------------------------------
diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
index 92c779764b27..672480f4f983 100644
--- a/arch/riscv/Kconfig.errata
+++ b/arch/riscv/Kconfig.errata
@@ -3,6 +3,7 @@ menu "CPU errata selection"
config ERRATA_ANDES
bool "Andes AX45MP errata"
depends on RISCV_ALTERNATIVE
+ depends on RISCV_SBI
help
All Andes errata Kconfig depend on this Kconfig. Disabling
this Kconfig will disable all Andes errata. Please say "Y"
@@ -12,7 +13,7 @@ config ERRATA_ANDES
config ERRATA_ANDES_CMO
bool "Apply Andes cache management errata"
- depends on ERRATA_ANDES && MMU && ARCH_R9A07G043
+ depends on ERRATA_ANDES && MMU
select RISCV_DMA_NONCOHERENT
default y
help
diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
index a57677f908f3..14d0ff5ec71b 100644
--- a/drivers/cache/Kconfig
+++ b/drivers/cache/Kconfig
@@ -3,7 +3,7 @@ menu "Cache Drivers"
config AX45MP_L2_CACHE
bool "Andes Technology AX45MP L2 Cache controller"
- depends on RISCV_DMA_NONCOHERENT
+ depends on ERRATA_ANDES_CMO
select RISCV_NONSTANDARD_CACHE_OPS
help
Support for the L2 cache controller on Andes Technology
AX45MP platforms.
diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index 67604f24973e..4f14fa149985 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -333,11 +333,9 @@ if RISCV
config ARCH_R9A07G043
bool "RISC-V Platform support for RZ/Five"
+ depends on AX45MP_L2_CACHE
select ARCH_RZG2L
- select AX45MP_L2_CACHE
select DMA_GLOBAL_POOL
- select ERRATA_ANDES
- select ERRATA_ANDES_CMO
help
This enables support for the Renesas RZ/Five SoC.
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [WARNING: ATTACHMENT UNSCANNED]Re: [linux-next:master 13230/13643] arch/riscv/errata/andes/errata.c:29:23: error: storage size of 'ret' isn't known
2023-08-31 11:53 ` Lad, Prabhakar
@ 2023-08-31 12:01 ` Geert Uytterhoeven
2023-08-31 13:01 ` Lad, Prabhakar
0 siblings, 1 reply; 11+ messages in thread
From: Geert Uytterhoeven @ 2023-08-31 12:01 UTC (permalink / raw)
To: Lad, Prabhakar
Cc: Conor Dooley, kernel test robot, Lad Prabhakar, oe-kbuild-all,
Linux Memory Management List, Palmer Dabbelt
Hi Prabhakar,
On Thu, Aug 31, 2023 at 1:54 PM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
> On Thu, Aug 31, 2023 at 12:34 PM Conor Dooley
> <conor.dooley@microchip.com> wrote:
> > On Thu, Aug 31, 2023 at 12:22:50PM +0100, Lad, Prabhakar wrote:
> > > On Thu, Aug 31, 2023 at 10:44 AM Conor Dooley
> > > <conor.dooley@microchip.com> wrote:
> > > >
> > > > On Thu, Aug 31, 2023 at 04:52:00PM +0800, kernel test robot wrote:
> > > > > tree: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
> > > > > head: a47fc304d2b678db1a5d760a7d644dac9b067752
> > > > > commit: f2863f30d1b05e5ecf61c063609cb974954d47f8 [13230/13643] riscv: errata: Add Andes alternative ports
> > > > > config: riscv-randconfig-001-20230831 (https://download.01.org/0day-ci/archive/20230831/202308311610.ec6bm2G8-lkp@intel.com/config)
> > > > > compiler: riscv64-linux-gcc (GCC) 13.2.0
> > > > > reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20230831/202308311610.ec6bm2G8-lkp@intel.com/reproduce)
> > > > >
> > > > > If you fix the issue in a separate patch/commit (i.e. not just a new version of
> > > > > the same patch/commit), kindly add following tags
> > > > > | Reported-by: kernel test robot <lkp@intel.com>
> > > > > | Closes: https://lore.kernel.org/oe-kbuild-all/202308311610.ec6bm2G8-lkp@intel.com/
> > > > >
> > > > > All error/warnings (new ones prefixed by >>):
> > > > >
> > > > > arch/riscv/errata/andes/errata.c: In function 'ax45mp_iocp_sw_workaround':
> > > > > >> arch/riscv/errata/andes/errata.c:29:23: error: storage size of 'ret' isn't known
> > > > > 29 | struct sbiret ret;
> > > > > | ^~~
> > > > > >> arch/riscv/errata/andes/errata.c:35:15: error: implicit declaration of function 'sbi_ecall' [-Werror=implicit-function-declaration]
> > > > > 35 | ret = sbi_ecall(ANDESTECH_SBI_EXT_ANDES, ANDES_SBI_EXT_IOCP_SW_WORKAROUND,
> > > > > | ^~~~~~~~~
> > > > > >> arch/riscv/errata/andes/errata.c:29:23: warning: unused variable 'ret' [-Wunused-variable]
> > > > > 29 | struct sbiret ret;
> > > > > | ^~~
> > > > > cc1: some warnings being treated as errors
> > > > >
> > > > >
> > > > > vim +29 arch/riscv/errata/andes/errata.c
> > > > >
> > > > > 26
> > > > > 27 static long ax45mp_iocp_sw_workaround(void)
> > > > > 28 {
> > > > > > 29 struct sbiret ret;
> > > > > 30
> > > > > 31 /*
> > > > > 32 * ANDES_SBI_EXT_IOCP_SW_WORKAROUND SBI EXT checks if the IOCP is missing and
> > > > > 33 * cache is controllable only then CMO will be applied to the platform.
> > > > > 34 */
> > > > > > 35 ret = sbi_ecall(ANDESTECH_SBI_EXT_ANDES, ANDES_SBI_EXT_IOCP_SW_WORKAROUND,
> > > > > 36 0, 0, 0, 0, 0, 0);
> > > > > 37
> > > > > 38 return ret.error ? 0 : ret.value;
> > > > > 39 }
> > > > > 40
> > > >
> > > > Looks like the config doesn't enable SBI, so ERRATA_ANDES_CMO will need
> > > > to grow a dependency on RISCV_SBI.
> > > I think adding dependency for RISCV_SBI on ERRATA_ANDES would be a good idea.
> > >
> > > While at it I am seeing below warnings with this randconfig:
> > > WARNING: unmet direct dependencies detected for ERRATA_ANDES_CMO
> > > Depends on [n]: ERRATA_ANDES [=y] && MMU [=n] && ARCH_R9A07G043 [=y]
So the issue is that CONFIG_MMU=n.
> --- a/arch/riscv/Kconfig.errata
> +++ b/arch/riscv/Kconfig.errata
> @@ -3,6 +3,7 @@ menu "CPU errata selection"
> config ERRATA_ANDES
> bool "Andes AX45MP errata"
> depends on RISCV_ALTERNATIVE
> + depends on RISCV_SBI
> help
> All Andes errata Kconfig depend on this Kconfig. Disabling
> this Kconfig will disable all Andes errata. Please say "Y"
> @@ -12,7 +13,7 @@ config ERRATA_ANDES
>
> config ERRATA_ANDES_CMO
> bool "Apply Andes cache management errata"
> - depends on ERRATA_ANDES && MMU && ARCH_R9A07G043
Why does this depend on MMU?
> + depends on ERRATA_ANDES && MMU
> select RISCV_DMA_NONCOHERENT
> default y
> help
> --- a/drivers/soc/renesas/Kconfig
> +++ b/drivers/soc/renesas/Kconfig
> @@ -333,11 +333,9 @@ if RISCV
>
> config ARCH_R9A07G043
> bool "RISC-V Platform support for RZ/Five"
> + depends on AX45MP_L2_CACHE
This looks backwards to me...
> select ARCH_RZG2L
> - select AX45MP_L2_CACHE
> select DMA_GLOBAL_POOL
> - select ERRATA_ANDES
> - select ERRATA_ANDES_CMO
> help
> This enables support for the Renesas RZ/Five SoC.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [WARNING: ATTACHMENT UNSCANNED]Re: [linux-next:master 13230/13643] arch/riscv/errata/andes/errata.c:29:23: error: storage size of 'ret' isn't known
2023-08-31 12:01 ` Geert Uytterhoeven
@ 2023-08-31 13:01 ` Lad, Prabhakar
2023-08-31 13:24 ` Geert Uytterhoeven
0 siblings, 1 reply; 11+ messages in thread
From: Lad, Prabhakar @ 2023-08-31 13:01 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Conor Dooley, kernel test robot, Lad Prabhakar, oe-kbuild-all,
Linux Memory Management List, Palmer Dabbelt
Hi Geert,
On Thu, Aug 31, 2023 at 1:01 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Thu, Aug 31, 2023 at 1:54 PM Lad, Prabhakar
> <prabhakar.csengg@gmail.com> wrote:
> > On Thu, Aug 31, 2023 at 12:34 PM Conor Dooley
> > <conor.dooley@microchip.com> wrote:
> > > On Thu, Aug 31, 2023 at 12:22:50PM +0100, Lad, Prabhakar wrote:
> > > > On Thu, Aug 31, 2023 at 10:44 AM Conor Dooley
> > > > <conor.dooley@microchip.com> wrote:
> > > > >
> > > > > On Thu, Aug 31, 2023 at 04:52:00PM +0800, kernel test robot wrote:
> > > > > > tree: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
> > > > > > head: a47fc304d2b678db1a5d760a7d644dac9b067752
> > > > > > commit: f2863f30d1b05e5ecf61c063609cb974954d47f8 [13230/13643] riscv: errata: Add Andes alternative ports
> > > > > > config: riscv-randconfig-001-20230831 (https://download.01.org/0day-ci/archive/20230831/202308311610.ec6bm2G8-lkp@intel.com/config)
> > > > > > compiler: riscv64-linux-gcc (GCC) 13.2.0
> > > > > > reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20230831/202308311610.ec6bm2G8-lkp@intel.com/reproduce)
> > > > > >
> > > > > > If you fix the issue in a separate patch/commit (i.e. not just a new version of
> > > > > > the same patch/commit), kindly add following tags
> > > > > > | Reported-by: kernel test robot <lkp@intel.com>
> > > > > > | Closes: https://lore.kernel.org/oe-kbuild-all/202308311610.ec6bm2G8-lkp@intel.com/
> > > > > >
> > > > > > All error/warnings (new ones prefixed by >>):
> > > > > >
> > > > > > arch/riscv/errata/andes/errata.c: In function 'ax45mp_iocp_sw_workaround':
> > > > > > >> arch/riscv/errata/andes/errata.c:29:23: error: storage size of 'ret' isn't known
> > > > > > 29 | struct sbiret ret;
> > > > > > | ^~~
> > > > > > >> arch/riscv/errata/andes/errata.c:35:15: error: implicit declaration of function 'sbi_ecall' [-Werror=implicit-function-declaration]
> > > > > > 35 | ret = sbi_ecall(ANDESTECH_SBI_EXT_ANDES, ANDES_SBI_EXT_IOCP_SW_WORKAROUND,
> > > > > > | ^~~~~~~~~
> > > > > > >> arch/riscv/errata/andes/errata.c:29:23: warning: unused variable 'ret' [-Wunused-variable]
> > > > > > 29 | struct sbiret ret;
> > > > > > | ^~~
> > > > > > cc1: some warnings being treated as errors
> > > > > >
> > > > > >
> > > > > > vim +29 arch/riscv/errata/andes/errata.c
> > > > > >
> > > > > > 26
> > > > > > 27 static long ax45mp_iocp_sw_workaround(void)
> > > > > > 28 {
> > > > > > > 29 struct sbiret ret;
> > > > > > 30
> > > > > > 31 /*
> > > > > > 32 * ANDES_SBI_EXT_IOCP_SW_WORKAROUND SBI EXT checks if the IOCP is missing and
> > > > > > 33 * cache is controllable only then CMO will be applied to the platform.
> > > > > > 34 */
> > > > > > > 35 ret = sbi_ecall(ANDESTECH_SBI_EXT_ANDES, ANDES_SBI_EXT_IOCP_SW_WORKAROUND,
> > > > > > 36 0, 0, 0, 0, 0, 0);
> > > > > > 37
> > > > > > 38 return ret.error ? 0 : ret.value;
> > > > > > 39 }
> > > > > > 40
> > > > >
> > > > > Looks like the config doesn't enable SBI, so ERRATA_ANDES_CMO will need
> > > > > to grow a dependency on RISCV_SBI.
> > > > I think adding dependency for RISCV_SBI on ERRATA_ANDES would be a good idea.
> > > >
> > > > While at it I am seeing below warnings with this randconfig:
> > > > WARNING: unmet direct dependencies detected for ERRATA_ANDES_CMO
> > > > Depends on [n]: ERRATA_ANDES [=y] && MMU [=n] && ARCH_R9A07G043 [=y]
>
> So the issue is that CONFIG_MMU=n.
>
> > --- a/arch/riscv/Kconfig.errata
> > +++ b/arch/riscv/Kconfig.errata
> > @@ -3,6 +3,7 @@ menu "CPU errata selection"
> > config ERRATA_ANDES
> > bool "Andes AX45MP errata"
> > depends on RISCV_ALTERNATIVE
> > + depends on RISCV_SBI
> > help
> > All Andes errata Kconfig depend on this Kconfig. Disabling
> > this Kconfig will disable all Andes errata. Please say "Y"
> > @@ -12,7 +13,7 @@ config ERRATA_ANDES
> >
> > config ERRATA_ANDES_CMO
> > bool "Apply Andes cache management errata"
> > - depends on ERRATA_ANDES && MMU && ARCH_R9A07G043
>
> Why does this depend on MMU?
>
Currently ARCH_R9A07G043 selects DMA_GLOBAL_POOL and we have
RISCV_DMA_NONCOHERENT selecting DMA_DIRECT_REMAP which causes below
build issue when MMU is disabled:
kernel/dma/pool.c: In function 'atomic_pool_expand':
kernel/dma/pool.c:105:44: error: implicit declaration of function
'pgprot_dmacoherent' [-Werror=implicit-function-declaration]
105 |
pgprot_dmacoherent(PAGE_KERNEL),
| ^~~~~~~~~~~~~~~~~~
kernel/dma/pool.c:105:44: error: incompatible type for argument 3 of
'dma_common_contiguous_remap'
105 |
pgprot_dmacoherent(PAGE_KERNEL),
|
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| |
| int
In file included from kernel/dma/pool.c:8:
> > + depends on ERRATA_ANDES && MMU
> > select RISCV_DMA_NONCOHERENT
> > default y
> > help
>
> > --- a/drivers/soc/renesas/Kconfig
> > +++ b/drivers/soc/renesas/Kconfig
> > @@ -333,11 +333,9 @@ if RISCV
> >
> > config ARCH_R9A07G043
> > bool "RISC-V Platform support for RZ/Five"
> > + depends on AX45MP_L2_CACHE
>
> This looks backwards to me...
>
Ok, then how about going with the imply approach?
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [WARNING: ATTACHMENT UNSCANNED]Re: [linux-next:master 13230/13643] arch/riscv/errata/andes/errata.c:29:23: error: storage size of 'ret' isn't known
2023-08-31 13:01 ` Lad, Prabhakar
@ 2023-08-31 13:24 ` Geert Uytterhoeven
2023-08-31 14:59 ` Lad, Prabhakar
0 siblings, 1 reply; 11+ messages in thread
From: Geert Uytterhoeven @ 2023-08-31 13:24 UTC (permalink / raw)
To: Lad, Prabhakar
Cc: Conor Dooley, kernel test robot, Lad Prabhakar, oe-kbuild-all,
Linux Memory Management List, Palmer Dabbelt
Hi Prabhakar,
On Thu, Aug 31, 2023 at 3:02 PM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
> On Thu, Aug 31, 2023 at 1:01 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Thu, Aug 31, 2023 at 1:54 PM Lad, Prabhakar
> > <prabhakar.csengg@gmail.com> wrote:
> > > On Thu, Aug 31, 2023 at 12:34 PM Conor Dooley
> > > <conor.dooley@microchip.com> wrote:
> > > > On Thu, Aug 31, 2023 at 12:22:50PM +0100, Lad, Prabhakar wrote:
> > > > > On Thu, Aug 31, 2023 at 10:44 AM Conor Dooley
> > > > > <conor.dooley@microchip.com> wrote:
> > > > > >
> > > > > > On Thu, Aug 31, 2023 at 04:52:00PM +0800, kernel test robot wrote:
> > > > > > > tree: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
> > > > > > > head: a47fc304d2b678db1a5d760a7d644dac9b067752
> > > > > > > commit: f2863f30d1b05e5ecf61c063609cb974954d47f8 [13230/13643] riscv: errata: Add Andes alternative ports
> > > > > > > config: riscv-randconfig-001-20230831 (https://download.01.org/0day-ci/archive/20230831/202308311610.ec6bm2G8-lkp@intel.com/config)
> > > > > > > compiler: riscv64-linux-gcc (GCC) 13.2.0
> > > > > > > reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20230831/202308311610.ec6bm2G8-lkp@intel.com/reproduce)
> > > > > > >
> > > > > > > If you fix the issue in a separate patch/commit (i.e. not just a new version of
> > > > > > > the same patch/commit), kindly add following tags
> > > > > > > | Reported-by: kernel test robot <lkp@intel.com>
> > > > > > > | Closes: https://lore.kernel.org/oe-kbuild-all/202308311610.ec6bm2G8-lkp@intel.com/
> > > > > > >
> > > > > > > All error/warnings (new ones prefixed by >>):
> > > > > > >
> > > > > > > arch/riscv/errata/andes/errata.c: In function 'ax45mp_iocp_sw_workaround':
> > > > > > > >> arch/riscv/errata/andes/errata.c:29:23: error: storage size of 'ret' isn't known
> > > > > > > 29 | struct sbiret ret;
> > > > > > > | ^~~
> > > > > > > >> arch/riscv/errata/andes/errata.c:35:15: error: implicit declaration of function 'sbi_ecall' [-Werror=implicit-function-declaration]
> > > > > > > 35 | ret = sbi_ecall(ANDESTECH_SBI_EXT_ANDES, ANDES_SBI_EXT_IOCP_SW_WORKAROUND,
> > > > > > > | ^~~~~~~~~
> > > > > > > >> arch/riscv/errata/andes/errata.c:29:23: warning: unused variable 'ret' [-Wunused-variable]
> > > > > > > 29 | struct sbiret ret;
> > > > > > > | ^~~
> > > > > > > cc1: some warnings being treated as errors
> > > > > > >
> > > > > > >
> > > > > > > vim +29 arch/riscv/errata/andes/errata.c
> > > > > > >
> > > > > > > 26
> > > > > > > 27 static long ax45mp_iocp_sw_workaround(void)
> > > > > > > 28 {
> > > > > > > > 29 struct sbiret ret;
> > > > > > > 30
> > > > > > > 31 /*
> > > > > > > 32 * ANDES_SBI_EXT_IOCP_SW_WORKAROUND SBI EXT checks if the IOCP is missing and
> > > > > > > 33 * cache is controllable only then CMO will be applied to the platform.
> > > > > > > 34 */
> > > > > > > > 35 ret = sbi_ecall(ANDESTECH_SBI_EXT_ANDES, ANDES_SBI_EXT_IOCP_SW_WORKAROUND,
> > > > > > > 36 0, 0, 0, 0, 0, 0);
> > > > > > > 37
> > > > > > > 38 return ret.error ? 0 : ret.value;
> > > > > > > 39 }
> > > > > > > 40
> > > > > >
> > > > > > Looks like the config doesn't enable SBI, so ERRATA_ANDES_CMO will need
> > > > > > to grow a dependency on RISCV_SBI.
> > > > > I think adding dependency for RISCV_SBI on ERRATA_ANDES would be a good idea.
> > > > >
> > > > > While at it I am seeing below warnings with this randconfig:
> > > > > WARNING: unmet direct dependencies detected for ERRATA_ANDES_CMO
> > > > > Depends on [n]: ERRATA_ANDES [=y] && MMU [=n] && ARCH_R9A07G043 [=y]
> >
> > So the issue is that CONFIG_MMU=n.
> >
> > > --- a/arch/riscv/Kconfig.errata
> > > +++ b/arch/riscv/Kconfig.errata
> > > @@ -3,6 +3,7 @@ menu "CPU errata selection"
> > > config ERRATA_ANDES
> > > bool "Andes AX45MP errata"
> > > depends on RISCV_ALTERNATIVE
> > > + depends on RISCV_SBI
> > > help
> > > All Andes errata Kconfig depend on this Kconfig. Disabling
> > > this Kconfig will disable all Andes errata. Please say "Y"
> > > @@ -12,7 +13,7 @@ config ERRATA_ANDES
> > >
> > > config ERRATA_ANDES_CMO
> > > bool "Apply Andes cache management errata"
> > > - depends on ERRATA_ANDES && MMU && ARCH_R9A07G043
> >
> > Why does this depend on MMU?
> >
> Currently ARCH_R9A07G043 selects DMA_GLOBAL_POOL and we have
> RISCV_DMA_NONCOHERENT selecting DMA_DIRECT_REMAP which causes below
> build issue when MMU is disabled:
>
> kernel/dma/pool.c: In function 'atomic_pool_expand':
> kernel/dma/pool.c:105:44: error: implicit declaration of function
> 'pgprot_dmacoherent' [-Werror=implicit-function-declaration]
> 105 |
> pgprot_dmacoherent(PAGE_KERNEL),
> | ^~~~~~~~~~~~~~~~~~
> kernel/dma/pool.c:105:44: error: incompatible type for argument 3 of
> 'dma_common_contiguous_remap'
> 105 |
> pgprot_dmacoherent(PAGE_KERNEL),
> |
> ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> | |
> | int
> In file included from kernel/dma/pool.c:8:
Hmm, kernel/dma/mapping.c has its use of pgprot_dmacoherent() inside
an #ifdef CONFIG_MMU block.
kernel/dma/pool.c has it inside an #ifdef CONFIG_DMA_DIRECT_REMAP block.
I guess that select should get a dependency on MMU:
config RISCV_DMA_NONCOHERENT
select DMA_DIRECT_REMAP if MMU
For comparison, m68k does take that into account:
select DMA_DIRECT_REMAP if HAS_DMA && MMU && !COLDFIRE
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [WARNING: ATTACHMENT UNSCANNED]Re: [linux-next:master 13230/13643] arch/riscv/errata/andes/errata.c:29:23: error: storage size of 'ret' isn't known
2023-08-31 13:24 ` Geert Uytterhoeven
@ 2023-08-31 14:59 ` Lad, Prabhakar
2023-08-31 16:36 ` Conor Dooley
0 siblings, 1 reply; 11+ messages in thread
From: Lad, Prabhakar @ 2023-08-31 14:59 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Conor Dooley, kernel test robot, Lad Prabhakar, oe-kbuild-all,
Linux Memory Management List, Palmer Dabbelt
Hi Geert,
On Thu, Aug 31, 2023 at 2:24 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Thu, Aug 31, 2023 at 3:02 PM Lad, Prabhakar
> <prabhakar.csengg@gmail.com> wrote:
> > On Thu, Aug 31, 2023 at 1:01 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > On Thu, Aug 31, 2023 at 1:54 PM Lad, Prabhakar
> > > <prabhakar.csengg@gmail.com> wrote:
> > > > On Thu, Aug 31, 2023 at 12:34 PM Conor Dooley
> > > > <conor.dooley@microchip.com> wrote:
> > > > > On Thu, Aug 31, 2023 at 12:22:50PM +0100, Lad, Prabhakar wrote:
> > > > > > On Thu, Aug 31, 2023 at 10:44 AM Conor Dooley
> > > > > > <conor.dooley@microchip.com> wrote:
<snip>
> > Currently ARCH_R9A07G043 selects DMA_GLOBAL_POOL and we have
> > RISCV_DMA_NONCOHERENT selecting DMA_DIRECT_REMAP which causes below
> > build issue when MMU is disabled:
> >
> > kernel/dma/pool.c: In function 'atomic_pool_expand':
> > kernel/dma/pool.c:105:44: error: implicit declaration of function
> > 'pgprot_dmacoherent' [-Werror=implicit-function-declaration]
> > 105 |
> > pgprot_dmacoherent(PAGE_KERNEL),
> > | ^~~~~~~~~~~~~~~~~~
> > kernel/dma/pool.c:105:44: error: incompatible type for argument 3 of
> > 'dma_common_contiguous_remap'
> > 105 |
> > pgprot_dmacoherent(PAGE_KERNEL),
> > |
> > ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> > | |
> > | int
> > In file included from kernel/dma/pool.c:8:
>
> Hmm, kernel/dma/mapping.c has its use of pgprot_dmacoherent() inside
> an #ifdef CONFIG_MMU block.
> kernel/dma/pool.c has it inside an #ifdef CONFIG_DMA_DIRECT_REMAP block.
>
> I guess that select should get a dependency on MMU:
>
> config RISCV_DMA_NONCOHERENT
> select DMA_DIRECT_REMAP if MMU
>
> For comparison, m68k does take that into account:
>
> select DMA_DIRECT_REMAP if HAS_DMA && MMU && !COLDFIRE
>
Thanks for the pointer. With this changes we dont get an unmet
dependencies warning.
arch/riscv/errata/andes/errata.c: In function 'ax45mp_iocp_sw_workaround':
arch/riscv/errata/andes/errata.c:29:23: error: storage size of 'ret' isn't known
29 | struct sbiret ret;
| ^~~
arch/riscv/errata/andes/errata.c:35:15: error: implicit declaration of
function 'sbi_ecall' [-Werror=implicit-function-declaration]
35 | ret = sbi_ecall(ANDESTECH_SBI_EXT_ANDES,
ANDES_SBI_EXT_IOCP_SW_WORKAROUND,
| ^~~~~~~~~
arch/riscv/errata/andes/errata.c:29:23: warning: unused variable 'ret'
[-Wunused-variable]
29 | struct sbiret ret;
| ^~~
arch/riscv/errata/andes/errata.c:39:1: error: control reaches end of
non-void function [-Werror=return-type]
39 | }
| ^
cc1: some warnings being treated as errors
To fix the above build issue reported by the bot, adding a dependency
for RISCV_SBI in ERRATA_ANDES won't help as ARCH_R9A07G043 is
explicitly selecting it. To avoid imply should explicitly select based
on dependency something like below?
diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
index 92c779764b27..566bcefeab50 100644
--- a/arch/riscv/Kconfig.errata
+++ b/arch/riscv/Kconfig.errata
@@ -2,7 +2,7 @@ menu "CPU errata selection"
config ERRATA_ANDES
bool "Andes AX45MP errata"
- depends on RISCV_ALTERNATIVE
+ depends on RISCV_ALTERNATIVE && RISCV_SBI
help
All Andes errata Kconfig depend on this Kconfig. Disabling
this Kconfig will disable all Andes errata. Please say "Y"
@@ -12,7 +12,7 @@ config ERRATA_ANDES
config ERRATA_ANDES_CMO
bool "Apply Andes cache management errata"
- depends on ERRATA_ANDES && MMU && ARCH_R9A07G043
+ depends on ERRATA_ANDES && ARCH_R9A07G043
select RISCV_DMA_NONCOHERENT
default y
help
diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index 67604f24973e..543300fe9862 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -334,10 +334,10 @@ if RISCV
config ARCH_R9A07G043
bool "RISC-V Platform support for RZ/Five"
select ARCH_RZG2L
- select AX45MP_L2_CACHE
+ select AX45MP_L2_CACHE if RISCV_DMA_NONCOHERENT
select DMA_GLOBAL_POOL
- select ERRATA_ANDES
- select ERRATA_ANDES_CMO
+ select ERRATA_ANDES if RISCV_SBI
+ select ERRATA_ANDES_CMO if ERRATA_ANDES
help
This enables support for the Renesas RZ/Five SoC.
Or am I missing a simpler way to fix this.
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [WARNING: ATTACHMENT UNSCANNED]Re: [linux-next:master 13230/13643] arch/riscv/errata/andes/errata.c:29:23: error: storage size of 'ret' isn't known
2023-08-31 14:59 ` Lad, Prabhakar
@ 2023-08-31 16:36 ` Conor Dooley
2023-09-01 8:34 ` Lad, Prabhakar
0 siblings, 1 reply; 11+ messages in thread
From: Conor Dooley @ 2023-08-31 16:36 UTC (permalink / raw)
To: Lad, Prabhakar
Cc: Geert Uytterhoeven, Conor Dooley, kernel test robot,
Lad Prabhakar, oe-kbuild-all, Linux Memory Management List,
Palmer Dabbelt
[-- Attachment #1: Type: text/plain, Size: 4277 bytes --]
On Thu, Aug 31, 2023 at 03:59:37PM +0100, Lad, Prabhakar wrote:
> > > Currently ARCH_R9A07G043 selects DMA_GLOBAL_POOL and we have
> > > RISCV_DMA_NONCOHERENT selecting DMA_DIRECT_REMAP which causes below
> > > build issue when MMU is disabled:
> > >
> > > kernel/dma/pool.c: In function 'atomic_pool_expand':
> > > kernel/dma/pool.c:105:44: error: implicit declaration of function
> > > 'pgprot_dmacoherent' [-Werror=implicit-function-declaration]
> > > 105 |
> > > pgprot_dmacoherent(PAGE_KERNEL),
> > > | ^~~~~~~~~~~~~~~~~~
> > > kernel/dma/pool.c:105:44: error: incompatible type for argument 3 of
> > > 'dma_common_contiguous_remap'
> > > 105 |
> > > pgprot_dmacoherent(PAGE_KERNEL),
> > > |
> > > ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> > > | |
> > > | int
> > > In file included from kernel/dma/pool.c:8:
> >
> > Hmm, kernel/dma/mapping.c has its use of pgprot_dmacoherent() inside
> > an #ifdef CONFIG_MMU block.
> > kernel/dma/pool.c has it inside an #ifdef CONFIG_DMA_DIRECT_REMAP block.
> >
> > I guess that select should get a dependency on MMU:
> >
> > config RISCV_DMA_NONCOHERENT
> > select DMA_DIRECT_REMAP if MMU
> >
> > For comparison, m68k does take that into account:
> >
> > select DMA_DIRECT_REMAP if HAS_DMA && MMU && !COLDFIRE
> >
> Thanks for the pointer. With this changes we dont get an unmet
> dependencies warning.
>
> arch/riscv/errata/andes/errata.c: In function 'ax45mp_iocp_sw_workaround':
> arch/riscv/errata/andes/errata.c:29:23: error: storage size of 'ret' isn't known
> 29 | struct sbiret ret;
> | ^~~
> arch/riscv/errata/andes/errata.c:35:15: error: implicit declaration of
> function 'sbi_ecall' [-Werror=implicit-function-declaration]
> 35 | ret = sbi_ecall(ANDESTECH_SBI_EXT_ANDES,
> ANDES_SBI_EXT_IOCP_SW_WORKAROUND,
> | ^~~~~~~~~
> arch/riscv/errata/andes/errata.c:29:23: warning: unused variable 'ret'
> [-Wunused-variable]
> 29 | struct sbiret ret;
> | ^~~
> arch/riscv/errata/andes/errata.c:39:1: error: control reaches end of
> non-void function [-Werror=return-type]
> 39 | }
> | ^
> cc1: some warnings being treated as errors
>
> To fix the above build issue reported by the bot, adding a dependency
> for RISCV_SBI in ERRATA_ANDES won't help as ARCH_R9A07G043 is
> explicitly selecting it. To avoid imply should explicitly select based
> on dependency something like below?
>
> diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
> index 92c779764b27..566bcefeab50 100644
> --- a/arch/riscv/Kconfig.errata
> +++ b/arch/riscv/Kconfig.errata
> @@ -2,7 +2,7 @@ menu "CPU errata selection"
>
> config ERRATA_ANDES
> bool "Andes AX45MP errata"
> - depends on RISCV_ALTERNATIVE
> + depends on RISCV_ALTERNATIVE && RISCV_SBI
> help
> All Andes errata Kconfig depend on this Kconfig. Disabling
> this Kconfig will disable all Andes errata. Please say "Y"
> @@ -12,7 +12,7 @@ config ERRATA_ANDES
>
> config ERRATA_ANDES_CMO
> bool "Apply Andes cache management errata"
> - depends on ERRATA_ANDES && MMU && ARCH_R9A07G043
> + depends on ERRATA_ANDES && ARCH_R9A07G043
> select RISCV_DMA_NONCOHERENT
> default y
> help
> diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
> index 67604f24973e..543300fe9862 100644
> --- a/drivers/soc/renesas/Kconfig
> +++ b/drivers/soc/renesas/Kconfig
> @@ -334,10 +334,10 @@ if RISCV
> config ARCH_R9A07G043
> bool "RISC-V Platform support for RZ/Five"
> select ARCH_RZG2L
> - select AX45MP_L2_CACHE
> + select AX45MP_L2_CACHE if RISCV_DMA_NONCOHERENT
> select DMA_GLOBAL_POOL
> - select ERRATA_ANDES
> - select ERRATA_ANDES_CMO
> + select ERRATA_ANDES if RISCV_SBI
> + select ERRATA_ANDES_CMO if ERRATA_ANDES
> help
> This enables support for the Renesas RZ/Five SoC.
>
> Or am I missing a simpler way to fix this.
This seems reasonable to me at least /shrug
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [WARNING: ATTACHMENT UNSCANNED]Re: [linux-next:master 13230/13643] arch/riscv/errata/andes/errata.c:29:23: error: storage size of 'ret' isn't known
2023-08-31 16:36 ` Conor Dooley
@ 2023-09-01 8:34 ` Lad, Prabhakar
0 siblings, 0 replies; 11+ messages in thread
From: Lad, Prabhakar @ 2023-09-01 8:34 UTC (permalink / raw)
To: Conor Dooley
Cc: Geert Uytterhoeven, Conor Dooley, kernel test robot,
Lad Prabhakar, oe-kbuild-all, Linux Memory Management List,
Palmer Dabbelt
Hi Conor,
On Thu, Aug 31, 2023 at 5:36 PM Conor Dooley <conor@kernel.org> wrote:
>
> On Thu, Aug 31, 2023 at 03:59:37PM +0100, Lad, Prabhakar wrote:
>
> > > > Currently ARCH_R9A07G043 selects DMA_GLOBAL_POOL and we have
> > > > RISCV_DMA_NONCOHERENT selecting DMA_DIRECT_REMAP which causes below
> > > > build issue when MMU is disabled:
> > > >
> > > > kernel/dma/pool.c: In function 'atomic_pool_expand':
> > > > kernel/dma/pool.c:105:44: error: implicit declaration of function
> > > > 'pgprot_dmacoherent' [-Werror=implicit-function-declaration]
> > > > 105 |
> > > > pgprot_dmacoherent(PAGE_KERNEL),
> > > > | ^~~~~~~~~~~~~~~~~~
> > > > kernel/dma/pool.c:105:44: error: incompatible type for argument 3 of
> > > > 'dma_common_contiguous_remap'
> > > > 105 |
> > > > pgprot_dmacoherent(PAGE_KERNEL),
> > > > |
> > > > ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> > > > | |
> > > > | int
> > > > In file included from kernel/dma/pool.c:8:
> > >
> > > Hmm, kernel/dma/mapping.c has its use of pgprot_dmacoherent() inside
> > > an #ifdef CONFIG_MMU block.
> > > kernel/dma/pool.c has it inside an #ifdef CONFIG_DMA_DIRECT_REMAP block.
> > >
> > > I guess that select should get a dependency on MMU:
> > >
> > > config RISCV_DMA_NONCOHERENT
> > > select DMA_DIRECT_REMAP if MMU
> > >
> > > For comparison, m68k does take that into account:
> > >
> > > select DMA_DIRECT_REMAP if HAS_DMA && MMU && !COLDFIRE
> > >
> > Thanks for the pointer. With this changes we dont get an unmet
> > dependencies warning.
> >
> > arch/riscv/errata/andes/errata.c: In function 'ax45mp_iocp_sw_workaround':
> > arch/riscv/errata/andes/errata.c:29:23: error: storage size of 'ret' isn't known
> > 29 | struct sbiret ret;
> > | ^~~
> > arch/riscv/errata/andes/errata.c:35:15: error: implicit declaration of
> > function 'sbi_ecall' [-Werror=implicit-function-declaration]
> > 35 | ret = sbi_ecall(ANDESTECH_SBI_EXT_ANDES,
> > ANDES_SBI_EXT_IOCP_SW_WORKAROUND,
> > | ^~~~~~~~~
> > arch/riscv/errata/andes/errata.c:29:23: warning: unused variable 'ret'
> > [-Wunused-variable]
> > 29 | struct sbiret ret;
> > | ^~~
> > arch/riscv/errata/andes/errata.c:39:1: error: control reaches end of
> > non-void function [-Werror=return-type]
> > 39 | }
> > | ^
> > cc1: some warnings being treated as errors
> >
> > To fix the above build issue reported by the bot, adding a dependency
> > for RISCV_SBI in ERRATA_ANDES won't help as ARCH_R9A07G043 is
> > explicitly selecting it. To avoid imply should explicitly select based
> > on dependency something like below?
> >
> > diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
> > index 92c779764b27..566bcefeab50 100644
> > --- a/arch/riscv/Kconfig.errata
> > +++ b/arch/riscv/Kconfig.errata
> > @@ -2,7 +2,7 @@ menu "CPU errata selection"
> >
> > config ERRATA_ANDES
> > bool "Andes AX45MP errata"
> > - depends on RISCV_ALTERNATIVE
> > + depends on RISCV_ALTERNATIVE && RISCV_SBI
> > help
> > All Andes errata Kconfig depend on this Kconfig. Disabling
> > this Kconfig will disable all Andes errata. Please say "Y"
> > @@ -12,7 +12,7 @@ config ERRATA_ANDES
> >
> > config ERRATA_ANDES_CMO
> > bool "Apply Andes cache management errata"
> > - depends on ERRATA_ANDES && MMU && ARCH_R9A07G043
> > + depends on ERRATA_ANDES && ARCH_R9A07G043
> > select RISCV_DMA_NONCOHERENT
> > default y
> > help
> > diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
> > index 67604f24973e..543300fe9862 100644
> > --- a/drivers/soc/renesas/Kconfig
> > +++ b/drivers/soc/renesas/Kconfig
> > @@ -334,10 +334,10 @@ if RISCV
> > config ARCH_R9A07G043
> > bool "RISC-V Platform support for RZ/Five"
> > select ARCH_RZG2L
> > - select AX45MP_L2_CACHE
> > + select AX45MP_L2_CACHE if RISCV_DMA_NONCOHERENT
> > select DMA_GLOBAL_POOL
> > - select ERRATA_ANDES
> > - select ERRATA_ANDES_CMO
> > + select ERRATA_ANDES if RISCV_SBI
> > + select ERRATA_ANDES_CMO if ERRATA_ANDES
> > help
> > This enables support for the Renesas RZ/Five SoC.
> >
> > Or am I missing a simpler way to fix this.
>
> This seems reasonable to me at least /shrug
>
Ok I will go this approach then.
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2023-09-01 8:35 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
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2023-08-31 8:52 [linux-next:master 13230/13643] arch/riscv/errata/andes/errata.c:29:23: error: storage size of 'ret' isn't known kernel test robot
2023-08-31 9:16 ` [WARNING: ATTACHMENT UNSCANNED]Re: " Conor Dooley
2023-08-31 11:22 ` Lad, Prabhakar
2023-08-31 11:33 ` Conor Dooley
2023-08-31 11:53 ` Lad, Prabhakar
2023-08-31 12:01 ` Geert Uytterhoeven
2023-08-31 13:01 ` Lad, Prabhakar
2023-08-31 13:24 ` Geert Uytterhoeven
2023-08-31 14:59 ` Lad, Prabhakar
2023-08-31 16:36 ` Conor Dooley
2023-09-01 8:34 ` Lad, Prabhakar
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