From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-f48.google.com (mail-wm0-f48.google.com [74.125.82.48]) by kanga.kvack.org (Postfix) with ESMTP id 98AFC6B0009 for ; Fri, 29 Jan 2016 19:35:37 -0500 (EST) Received: by mail-wm0-f48.google.com with SMTP id r129so1465535wmr.0 for ; Fri, 29 Jan 2016 16:35:37 -0800 (PST) Received: from mail-wm0-x243.google.com (mail-wm0-x243.google.com. [2a00:1450:400c:c09::243]) by mx.google.com with ESMTPS id j13si262456wmd.85.2016.01.29.16.35.36 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 29 Jan 2016 16:35:36 -0800 (PST) Received: by mail-wm0-x243.google.com with SMTP id 128so201102wmz.3 for ; Fri, 29 Jan 2016 16:35:36 -0800 (PST) MIME-Version: 1.0 In-Reply-To: <20160114043956.GA8496@pd.tnic> References: <20160110112635.GC22896@pd.tnic> <20160111104425.GA29448@gmail.com> <20160114043956.GA8496@pd.tnic> Date: Fri, 29 Jan 2016 16:35:35 -0800 Message-ID: Subject: Re: [PATCH v8 3/3] x86, mce: Add __mcsafe_copy() From: Tony Luck Content-Type: text/plain; charset=UTF-8 Sender: owner-linux-mm@kvack.org List-ID: To: Borislav Petkov Cc: Ingo Molnar , Dan Williams , Andy Lutomirski , linux-nvdimm , "linux-kernel@vger.kernel.org" , Andrew Morton , Robert , "linux-mm@kvack.org" , X86 ML On Wed, Jan 13, 2016 at 8:39 PM, Borislav Petkov wrote: > On Wed, Jan 13, 2016 at 03:22:58PM -0800, Tony Luck wrote: >> Are there some examples of synthetic CPUID bits? > > X86_FEATURE_ALWAYS is one. The others got renamed into X86_BUG_* ones, > the remaining mechanism is the same, though. So something like this [gmail will line wrap, but should still be legible] Then Dan will be able to use: if (cpu_has(c, X86_FEATURE_MCRECOVERY)) to decide whether to use the (slightly slower, but recovery capable) __mcsafe_copy() or just pick the fastest memcpy() instead. -Tony diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index 7ad8c9464297..621e05103633 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -106,6 +106,7 @@ #define X86_FEATURE_APERFMPERF ( 3*32+28) /* APERFMPERF */ #define X86_FEATURE_EAGER_FPU ( 3*32+29) /* "eagerfpu" Non lazy FPU restore */ #define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in S3 state */ +#define X86_FEATURE_MCRECOVERY ( 3*32+31) /* cpu has recoverable machine checks */ /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ #define X86_FEATURE_XMM3 ( 4*32+ 0) /* "pni" SSE-3 */ diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c index a006f4cd792b..b8980d767240 100644 --- a/arch/x86/kernel/cpu/mcheck/mce.c +++ b/arch/x86/kernel/cpu/mcheck/mce.c @@ -1694,6 +1694,14 @@ void mcheck_cpu_init(struct cpuinfo_x86 *c) return; } + /* + * MCG_CAP.MCG_SER_P is necessary but not sufficient to know + * whether this processor will actually generate recoverable + * machine checks. Check to see if this is an E7 model Xeon. + */ + if (mca_cfg.ser && !strncmp(c->x86_model_id, "Intel(R) Xeon(R) CPU E7-", 24)) + set_cpu_cap(c, X86_FEATURE_MCRECOVERY); + if (mce_gen_pool_init()) { mca_cfg.disabled = true; pr_emerg("Couldn't allocate MCE records pool!\n"); -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org