From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-vb0-f43.google.com (mail-vb0-f43.google.com [209.85.212.43]) by kanga.kvack.org (Postfix) with ESMTP id A74BB6B0036 for ; Fri, 22 Nov 2013 21:11:53 -0500 (EST) Received: by mail-vb0-f43.google.com with SMTP id q12so1380557vbe.2 for ; Fri, 22 Nov 2013 18:11:53 -0800 (PST) Received: from mail-ve0-x233.google.com (mail-ve0-x233.google.com [2607:f8b0:400c:c01::233]) by mx.google.com with ESMTPS id ug9si13585515vcb.32.2013.11.22.18.11.52 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 22 Nov 2013 18:11:52 -0800 (PST) Received: by mail-ve0-f179.google.com with SMTP id jw12so1452260veb.38 for ; Fri, 22 Nov 2013 18:11:52 -0800 (PST) MIME-Version: 1.0 In-Reply-To: <20131123013654.GG4138@linux.vnet.ibm.com> References: <20131122184937.GX4138@linux.vnet.ibm.com> <20131122200620.GA4138@linux.vnet.ibm.com> <20131122203738.GC4138@linux.vnet.ibm.com> <20131122215208.GD4138@linux.vnet.ibm.com> <20131123002542.GF4138@linux.vnet.ibm.com> <20131123013654.GG4138@linux.vnet.ibm.com> Date: Fri, 22 Nov 2013 18:11:52 -0800 Message-ID: Subject: Re: [PATCH v6 4/5] MCS Lock: Barrier corrections From: Linus Torvalds Content-Type: text/plain; charset=UTF-8 Sender: owner-linux-mm@kvack.org List-ID: To: Paul McKenney Cc: Ingo Molnar , Tim Chen , Will Deacon , Ingo Molnar , Andrew Morton , Thomas Gleixner , "linux-kernel@vger.kernel.org" , linux-mm , "linux-arch@vger.kernel.org" , Waiman Long , Andrea Arcangeli , Alex Shi , Andi Kleen , Michel Lespinasse , Davidlohr Bueso , Matthew R Wilcox , Dave Hansen , Peter Zijlstra , Rik van Riel , Peter Hurley , Raghavendra K T , George Spelvin , "H. Peter Anvin" , Arnd Bergmann , Aswin Chandramouleeswaran , Scott J Norton , "Figo.zhang" On Fri, Nov 22, 2013 at 5:36 PM, Paul E. McKenney wrote: > > So there is your example. It really can and does happen. > > Again, easy fix. Just change powerpc's smp_store_release() from lwsync > to smp_mb(). That fixes the problem and doesn't hurt anyone but powerpc. > > OK? Hmm. Ok Except now I'm worried it can happen on x86 too because my mental model was clearly wrong. x86 does have that extra "Memory ordering obeys causality (memory ordering respects transitive visibility)." rule, and the example in the architecture manual (section 8.2.3.6 "Stores Are Transitively Visible") seems to very much about this, but your particular example is subtly different, so.. I will have to ruminate on this. Linus -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org