From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-vb0-f52.google.com (mail-vb0-f52.google.com [209.85.212.52]) by kanga.kvack.org (Postfix) with ESMTP id 7A4486B0035 for ; Fri, 29 Nov 2013 11:44:43 -0500 (EST) Received: by mail-vb0-f52.google.com with SMTP id f13so6953873vbg.11 for ; Fri, 29 Nov 2013 08:44:43 -0800 (PST) Received: from mail-vb0-x22b.google.com (mail-vb0-x22b.google.com [2607:f8b0:400c:c02::22b]) by mx.google.com with ESMTPS id f20si25053868vcs.67.2013.11.29.08.44.42 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 29 Nov 2013 08:44:42 -0800 (PST) Received: by mail-vb0-f43.google.com with SMTP id q12so6834276vbe.16 for ; Fri, 29 Nov 2013 08:44:42 -0800 (PST) MIME-Version: 1.0 In-Reply-To: <20131129161711.GG31000@mudshark.cambridge.arm.com> References: <20131126225136.GG4137@linux.vnet.ibm.com> <20131127101613.GC9032@mudshark.cambridge.arm.com> <20131127171143.GN4137@linux.vnet.ibm.com> <20131128114058.GC21354@mudshark.cambridge.arm.com> <20131128173853.GV4137@linux.vnet.ibm.com> <20131128180318.GE16203@mudshark.cambridge.arm.com> <20131128182712.GW4137@linux.vnet.ibm.com> <20131128185341.GG16203@mudshark.cambridge.arm.com> <20131128195039.GX4137@linux.vnet.ibm.com> <20131129161711.GG31000@mudshark.cambridge.arm.com> Date: Fri, 29 Nov 2013 08:44:41 -0800 Message-ID: Subject: Re: [PATCH v6 4/5] MCS Lock: Barrier corrections From: Linus Torvalds Content-Type: multipart/alternative; boundary=001a11c3b1b0ff437704ec538b9e Sender: owner-linux-mm@kvack.org List-ID: To: Will Deacon Cc: Arnd Bergmann , "Figo. zhang" , Aswin Chandramouleeswaran , Rik van Riel , Waiman Long , "linux-kernel@vger.kernel.org" , Raghavendra K T , "linux-arch@vger.kernel.org" , Andi Kleen , George Spelvin , Tim Chen , Michel Lespinasse , Ingo Molnar , "Paul E. McKenney" , Peter Hurley , "H. Peter Anvin" , Andrew Morton , linux-mm , Alex Shi , Andrea Arcangeli , Scott J Norton , Thomas Gleixner , Dave Hansen , Peter Zijlstra , Matthew R Wilcox , Davidlohr Bueso --001a11c3b1b0ff437704ec538b9e Content-Type: text/plain; charset=UTF-8 On Nov 29, 2013 8:18 AM, "Will Deacon" wrote: > > To get some sort of > idea, I tried adding a dmb to the start of spin_unlock on ARMv7 and I saw a > 3% performance hit in hackbench on my dual-cluster board. Don't do a dmb. Just do a dummy release. You just said that on arm64 a unlock+lock is a memory barrier, so just make the mb__before_spinlock() be a dummy store with release to the stack.. That should be noticeably cheaper than a full dmb. Linus --001a11c3b1b0ff437704ec538b9e Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable


On Nov 29, 2013 8:18 AM, "Will Deacon" <will.deacon@arm.com> wrote:
>
>=C2=A0 To get some sort of
> idea, I tried adding a dmb to the start of spin_unlock on ARMv7 and I = saw a
> 3% performance hit in hackbench on my dual-cluster board.

Don't do a dmb. Just do a dummy release. You just said t= hat on arm64 a unlock+lock is a memory barrier, so just make the mb__before= _spinlock() be a dummy store with release to the stack..

That should be noticeably cheaper than a full dmb.

=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 Linus

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