Re: [PATCH v3 4/4] riscv: Improve flush_tlb_kernel_range()

[Nadav Amit <nadav.amit@gmail.com>]

> On Sep 6, 2023, at 4:48 AM, Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> 
> Hi Alexandre,
> 
> On Tue, Aug 1, 2023 at 9:58 AM Alexandre Ghiti <alexghiti@rivosinc.com> wrote:
>> 
>> This function used to simply flush the whole tlb of all harts, be more
>> subtile and try to only flush the range.
>> 
>> The problem is that we can only use PAGE_SIZE as stride since we don't know
>> the size of the underlying mapping and then this function will be improved
>> only if the size of the region to flush is < threshold * PAGE_SIZE.
>> 
>> Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
>> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
>> ---
>> arch/riscv/include/asm/tlbflush.h | 11 +++++-----
>> arch/riscv/mm/tlbflush.c          | 34 +++++++++++++++++++++++--------
>> 2 files changed, 31 insertions(+), 14 deletions(-)
>> 
> After applying this patch, I am seeing module load issues on RZ/Five
> (complete log [0]). I am testing defconfig + [1] (rz/five related
> configs).
> 
> Any pointers on what could be an issue here?

None of my business, but looking at your code, it seems that you do not memory
barrier before reading mm_cpumask() in __flush_tlb_range(). I believe you
would want to synchronize __flush_tlb_range with switch_mm() similarly to the
way it is done in x86.