From: John David Anglin <dave.anglin@bell.net>
To: Matthew Wilcox <willy@linux.intel.com>
Cc: linux-mm@kvack.org, "David S. Miller" <davem@davemloft.net>,
sparclinux@vger.kernel.org, linux-parisc@vger.kernel.org,
linux-mips@linux-mips.org
Subject: Re: [PATCH] remap_file_pages needs to check for cache coherency
Date: Fri, 27 Dec 2013 14:47:32 -0500 [thread overview]
Message-ID: <BLU0-SMTP15241D603FEB77037F6D1E97CD0@phx.gbl> (raw)
In-Reply-To: <20131227193330.GE4945@linux.intel.com>
On 27-Dec-13, at 2:33 PM, Matthew Wilcox wrote:
> Have you considered measuring SHMLBA on different CPU models and
> reducing it at boot time? I know that 4MB is the architectural
> guarantee
> (actually, I seem to remember that 16MB was the architectural
> guarantee,
> but jsm found some CPU architects who said it would enver exceed 4MB).
> I bet some CPUs have considerably lower cache coherency limits.
It's worth looking at. The value is supposed to be returned by the
PDC_CACHE PDC
call but I know my rp3440 returns a value of 0 indicating that the
aliasing boundary
is unknown and may be greater than 16MB.
Dave
--
John David Anglin dave.anglin@bell.net
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next prev parent reply other threads:[~2013-12-27 19:47 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-27 18:00 Matthew Wilcox
2013-12-27 18:48 ` David Miller
2013-12-27 19:20 ` Matthew Wilcox
2013-12-27 19:13 ` John David Anglin
2013-12-27 19:33 ` Matthew Wilcox
2013-12-27 19:47 ` John David Anglin [this message]
2013-12-27 20:14 ` John David Anglin
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