From: Nadav Amit <nadav.amit@gmail.com>
To: linux-mm@kvack.org
Subject: x86: possible store-tearing in native_set_pte?
Date: Mon, 25 Apr 2016 17:24:14 -0700 [thread overview]
Message-ID: <BB81219D-9DAC-4A88-8029-C40E8D69D708@gmail.com> (raw)
Can someone please explain why it is ok for native_set_pte to assign the PTE
without WRITE_ONCE() ?
Couldn’t a PTE write be torn, and the PTE be prefetched in between (or even
used for translation by another core)?
I did not encounter this case, but it seems to me possible according to the
documentation:
Intel SDM 4.10.2.3 “Detail of TLB Use": "The processor may cache
translations required for prefetches and for accesses ... that would never
actually occur in the executed code path.”
Documentation/memory-barriers.txt: "The compiler is within its rights to
invent stores to a variable”.
Thanks,
Nadav
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next reply other threads:[~2016-04-26 0:24 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-04-26 0:24 Nadav Amit [this message]
2016-04-26 0:40 ` Nadav Amit
2016-05-16 14:18 ` Vlastimil Babka
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