From: Nick Piggin <npiggin@gmail.com>
To: Rik van Riel <riel@redhat.com>
Cc: Ying Han <yinghan@google.com>,
linux-mm@kvack.org, Hugh Dickins <hughd@google.com>,
Minchan Kim <minchan.kim@gmail.com>,
KAMEZAWA Hiroyuki <kamezawa.hiroyu@jp.fujitsu.com>,
Andrew Morton <akpm@linux-foundation.org>
Subject: Re: [PATCH] mm: don't flush TLB when propagate PTE access bit to struct page.
Date: Wed, 27 Oct 2010 12:37:31 -0600 [thread overview]
Message-ID: <AANLkTimLBO7mJugVXH0S=QSnwQ+NDcz3zxmcHmPRjngd@mail.gmail.com> (raw)
In-Reply-To: <AANLkTikL+v6uzkXg-7J2FGVz-7kc0Myw_cO5s_wYfHHm@mail.gmail.com>
On Wed, Oct 27, 2010 at 12:22 PM, Nick Piggin <npiggin@gmail.com> wrote:
> On Wed, Oct 27, 2010 at 12:05 PM, Rik van Riel <riel@redhat.com> wrote:
>> On 10/27/2010 01:21 PM, Ying Han wrote:
>>>
>>> kswapd's use case of hardware PTE accessed bit is to approximate page LRU.
>>> The
>>> ActiveLRU demotion to InactiveLRU are not base on accessed bit, while it
>>> is only
>>> used to promote when a page is on inactive LRU list. All of the state
>>> transitions
>>> are triggered by memory pressure and thus has weak relationship with
>>> respect to
>>> time. In addition, hardware already transparently flush tlb whenever CPU
>>> context
>>> switch processes and given limited hardware TLB resource, the time period
>>> in
>>> which a page is accessed but not yet propagated to struct page is very
>>> small
>>> in practice. With the nature of approximation, kernel really don't need to
>>> flush TLB
>>> for changing PTE's access bit. This commit removes the flush operation
>>> from it.
>>>
>>> Signed-off-by: Ying Han<yinghan@google.com>
>>> Singed-off-by: Ken Chen<kenchen@google.com>
>>
>> The reasoning behind the patch makes sense.
>>
>> However, have you measured any improvements in run time with
>> this patch? The VM is already tweaked to minimize the number
>> of pages that get aged, so it would be interesting to know
>> where you saw issues.
>
> Firstly, not all CPUs do flush the TLB on VM switch, and secondly, it
> would be theoretically possible to spin and never be able to flush free
> pages even if none are ever being touched.
>
> It doesn't have to be an absurdly tiny machine, either. You could cover
> a good few megs with TLBs (and a small embedded system could easily
> have less than that of mapped memory on its LRU).
>
> I agree the theory is fine because if the CPU thinks it is worth to keep a
> TLB entry around, then it probably knows better than our stupid LRU :)
> And TLB flushing can get nasty when we start swapping a lot with
> threaded apps.
>
> However, to handle corner cases it should either:
>
> flush all TLBs once per *something* [eg. every scan priority level above N,
> or every N pages scanned, etc]
>
> start doing the flush versions of the ptep manipulation when memory
> pressure is getting high.
>
I'm sorry, that's absurd, ignore that :)
However, it's a scary change -- higher chance of reclaiming a TLB covered page.
I had a vague memory of this problem biting someone when this flush wasn't
actually done properly... maybe powerpc.
But anyway, same solution could be possible, by flushing every N pages scanned.
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next prev parent reply other threads:[~2010-10-27 18:37 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-10-27 17:21 Ying Han
2010-10-27 18:05 ` Rik van Riel
2010-10-27 18:22 ` Nick Piggin
2010-10-27 18:37 ` Nick Piggin [this message]
2010-10-27 19:13 ` Hugh Dickins
2010-10-27 20:35 ` Ying Han
2010-10-28 0:11 ` KAMEZAWA Hiroyuki
2010-10-29 1:30 ` Ken Chen
2010-10-29 2:45 ` KAMEZAWA Hiroyuki
2010-10-29 3:43 ` Rik van Riel
2010-10-29 4:27 ` Minchan Kim
2010-10-29 12:31 ` Rik van Riel
2010-10-29 13:03 ` Minchan Kim
2010-10-29 13:15 ` Rik van Riel
2010-10-30 0:20 ` Minchan Kim
2010-10-27 20:19 ` Ying Han
2010-10-28 11:53 ` Rik van Riel
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