linux-mm.kvack.org archive mirror
 help / color / mirror / Atom feed
* [PATCH v4 1/2] Introduce cpu_icache_is_aliasing() across all architectures
@ 2024-12-07 17:16 Zi Yan
  2024-12-07 17:16 ` [PATCH v4 2/2] mm: use clear_user_(high)page() for arch with special user folio handling Zi Yan
  2024-12-09 18:07 ` [PATCH v4 1/2] Introduce cpu_icache_is_aliasing() across all architectures Vlastimil Babka
  0 siblings, 2 replies; 5+ messages in thread
From: Zi Yan @ 2024-12-07 17:16 UTC (permalink / raw)
  To: linux-mm, Andrew Morton, Geert Uytterhoeven, Mathieu Desnoyers
  Cc: Vlastimil Babka, David Hildenbrand, Matthew Wilcox (Oracle),
	Miaohe Lin, Kefeng Wang, John Hubbard, Huang, Ying, Ryan Roberts,
	Alexander Potapenko, Kees Cook, Vineet Gupta, linux-kernel,
	linux-snps-arc, Zi Yan

In commit eacd0e950dc2 ("ARC: [mm] Lazy D-cache flush (non aliasing
VIPT)"), arc adds the need to flush dcache to make icache see the code
page change. This also requires special handling for
clear_user_(high)page(). Introduce cpu_icache_is_aliasing() to make
MM code query special clear_user_(high)page() easier. This will be used
by the following commit.

Suggested-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Signed-off-by: Zi Yan <ziy@nvidia.com>
Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
---
 arch/arc/Kconfig                 | 1 +
 arch/arc/include/asm/cachetype.h | 8 ++++++++
 include/linux/cacheinfo.h        | 6 ++++++
 3 files changed, 15 insertions(+)
 create mode 100644 arch/arc/include/asm/cachetype.h

diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index 5b2488142041..e96935373796 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -6,6 +6,7 @@
 config ARC
 	def_bool y
 	select ARC_TIMERS
+	select ARCH_HAS_CPU_CACHE_ALIASING
 	select ARCH_HAS_CACHE_LINE_SIZE
 	select ARCH_HAS_DEBUG_VM_PGTABLE
 	select ARCH_HAS_DMA_PREP_COHERENT
diff --git a/arch/arc/include/asm/cachetype.h b/arch/arc/include/asm/cachetype.h
new file mode 100644
index 000000000000..acd3b6cb4bf5
--- /dev/null
+++ b/arch/arc/include/asm/cachetype.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_ARC_CACHETYPE_H
+#define __ASM_ARC_CACHETYPE_H
+
+#define cpu_dcache_is_aliasing()	false
+#define cpu_icache_is_aliasing()	true
+
+#endif
diff --git a/include/linux/cacheinfo.h b/include/linux/cacheinfo.h
index 108060612bb8..7ad736538649 100644
--- a/include/linux/cacheinfo.h
+++ b/include/linux/cacheinfo.h
@@ -155,8 +155,14 @@ static inline int get_cpu_cacheinfo_id(int cpu, int level)
 
 #ifndef CONFIG_ARCH_HAS_CPU_CACHE_ALIASING
 #define cpu_dcache_is_aliasing()	false
+#define cpu_icache_is_aliasing()	cpu_dcache_is_aliasing()
 #else
 #include <asm/cachetype.h>
+
+#ifndef cpu_icache_is_aliasing
+#define cpu_icache_is_aliasing()	cpu_dcache_is_aliasing()
+#endif
+
 #endif
 
 #endif /* _LINUX_CACHEINFO_H */
-- 
2.45.2



^ permalink raw reply	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2024-12-09 18:14 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-12-07 17:16 [PATCH v4 1/2] Introduce cpu_icache_is_aliasing() across all architectures Zi Yan
2024-12-07 17:16 ` [PATCH v4 2/2] mm: use clear_user_(high)page() for arch with special user folio handling Zi Yan
2024-12-09 18:12   ` Vlastimil Babka
2024-12-09 18:14     ` Zi Yan
2024-12-09 18:07 ` [PATCH v4 1/2] Introduce cpu_icache_is_aliasing() across all architectures Vlastimil Babka

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox