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([2601:646:c200:1ef2:2197:2a30:2ff8:e80a]) by smtp.gmail.com with ESMTPSA id o15sm427033pgi.74.2020.09.02.16.50.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 02 Sep 2020 16:50:34 -0700 (PDT) Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable From: Andy Lutomirski Mime-Version: 1.0 (1.0) Subject: Re: [PATCH v11 6/9] x86/cet: Add PTRACE interface for CET Date: Wed, 2 Sep 2020 16:50:32 -0700 Message-Id: References: <9be5356c-ec51-4541-89e5-05a1727a09a8@intel.com> Cc: Jann Horn , the arch/x86 maintainers , "H. Peter Anvin" , Thomas Gleixner , Ingo Molnar , kernel list , linux-doc@vger.kernel.org, Linux-MM , linux-arch , Linux API , Arnd Bergmann , Andy Lutomirski , Balbir Singh , Borislav Petkov , Cyrill Gorcunov , Dave Hansen , Eugene Syromiatnikov , Florian Weimer , "H.J. Lu" , Jonathan Corbet , Kees Cook , Mike Kravetz , Nadav Amit , Oleg Nesterov , Pavel Machek , Peter Zijlstra , Randy Dunlap , "Ravi V. Shankar" , Vedvyas Shanbhogue , Dave Martin , Weijiang Yang In-Reply-To: <9be5356c-ec51-4541-89e5-05a1727a09a8@intel.com> To: "Yu, Yu-cheng" X-Mailer: iPhone Mail (17G80) X-Rspamd-Queue-Id: 4C6C31804E3A8 X-Spamd-Result: default: False [0.00 / 100.00] X-Rspamd-Server: rspam01 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: > On Sep 2, 2020, at 3:13 PM, Yu, Yu-cheng wrote: >=20 > =EF=BB=BFOn 9/2/2020 1:03 PM, Jann Horn wrote: >>> On Tue, Aug 25, 2020 at 2:30 AM Yu-cheng Yu wrot= e: >>> Add REGSET_CET64/REGSET_CET32 to get/set CET MSRs: >>>=20 >>> IA32_U_CET (user-mode CET settings) and >>> IA32_PL3_SSP (user-mode Shadow Stack) >> [...] >>> diff --git a/arch/x86/kernel/fpu/regset.c b/arch/x86/kernel/fpu/regset.c= >> [...] >>> +int cetregs_get(struct task_struct *target, const struct user_regset *r= egset, >>> + struct membuf to) >>> +{ >>> + struct fpu *fpu =3D &target->thread.fpu; >>> + struct cet_user_state *cetregs; >>> + >>> + if (!boot_cpu_has(X86_FEATURE_SHSTK)) >>> + return -ENODEV; >>> + >>> + fpu__prepare_read(fpu); >>> + cetregs =3D get_xsave_addr(&fpu->state.xsave, XFEATURE_CET_USER)= ; >>> + if (!cetregs) >>> + return -EFAULT; >> Can this branch ever be hit without a kernel bug? If yes, I think >> -EFAULT is probably a weird error code to choose here. If no, this >> should probably use WARN_ON(). Same thing in cetregs_set(). >=20 > When a thread is not CET-enabled, its CET state does not exist. I looked a= t EFAULT, and it means "Bad address". Maybe this can be ENODEV, which means= "No such device"? >=20 > [...] >=20 >>> @@ -1284,6 +1293,13 @@ static struct user_regset x86_32_regsets[] __ro_a= fter_init =3D { >> [...] >>> + [REGSET_CET32] =3D { >>> + .core_note_type =3D NT_X86_CET, >>> + .n =3D sizeof(struct cet_user_state) / sizeof(u64), >>> + .size =3D sizeof(u64), .align =3D sizeof(u64), >>> + .active =3D cetregs_active, .regset_get =3D cetregs_get,= >>> + .set =3D cetregs_set >>> + }, >>> }; >> Why are there different identifiers for 32-bit CET and 64-bit CET when >> they operate on the same structs and have the same handlers? If >> there's a good reason for that, the commit message should probably >> point that out. >=20 > Yes, the reason for two regsets is that fill_note_info() does not expect a= ny holes in a regsets. I will put this in the commit log. >=20 >=20 Perhaps we could fix that instead?=