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([2600:1012:b044:6f30:60ea:7662:8055:2cca]) by smtp.gmail.com with ESMTPSA id b2sm2609638pgk.50.2019.06.07.10.05.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 07 Jun 2019 10:05:15 -0700 (PDT) Content-Type: text/plain; charset=utf-8 Mime-Version: 1.0 (1.0) Subject: Re: [PATCH v7 03/14] x86/cet/ibt: Add IBT legacy code bitmap setup function From: Andy Lutomirski X-Mailer: iPhone Mail (16F203) In-Reply-To: Date: Fri, 7 Jun 2019 10:05:13 -0700 Cc: Peter Zijlstra , x86@kernel.org, "H. Peter Anvin" , Thomas Gleixner , Ingo Molnar , linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-api@vger.kernel.org, Arnd Bergmann , Balbir Singh , Borislav Petkov , Cyrill Gorcunov , Dave Hansen , Eugene Syromiatnikov , Florian Weimer , "H.J. Lu" , Jann Horn , Jonathan Corbet , Kees Cook , Mike Kravetz , Nadav Amit , Oleg Nesterov , Pavel Machek , Randy Dunlap , "Ravi V. Shankar" , Vedvyas Shanbhogue , Dave Martin Content-Transfer-Encoding: quoted-printable Message-Id: References: <20190606200926.4029-1-yu-cheng.yu@intel.com> <20190606200926.4029-4-yu-cheng.yu@intel.com> <20190607080832.GT3419@hirez.programming.kicks-ass.net> <76B7B1AE-3AEA-4162-B539-990EF3CCE2C2@amacapital.net> To: Yu-cheng Yu X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: > On Jun 7, 2019, at 9:45 AM, Yu-cheng Yu wrote: >=20 > On Fri, 2019-06-07 at 09:35 -0700, Andy Lutomirski wrote: >>> On Jun 7, 2019, at 9:23 AM, Yu-cheng Yu wrote: >>>=20 >>>>> On Fri, 2019-06-07 at 10:08 +0200, Peter Zijlstra wrote: >>>>> On Thu, Jun 06, 2019 at 01:09:15PM -0700, Yu-cheng Yu wrote: >>>>> Indirect Branch Tracking (IBT) provides an optional legacy code bitmap= >>>>> that allows execution of legacy, non-IBT compatible library by an >>>>> IBT-enabled application. When set, each bit in the bitmap indicates >>>>> one page of legacy code. >>>>>=20 >>>>> The bitmap is allocated and setup from the application. >>>>> +int cet_setup_ibt_bitmap(unsigned long bitmap, unsigned long size) >>>>> +{ >>>>> + u64 r; >>>>> + >>>>> + if (!current->thread.cet.ibt_enabled) >>>>> + return -EINVAL; >>>>> + >>>>> + if (!PAGE_ALIGNED(bitmap) || (size > TASK_SIZE_MAX)) >>>>> + return -EINVAL; >>>>> + >>>>> + current->thread.cet.ibt_bitmap_addr =3D bitmap; >>>>> + current->thread.cet.ibt_bitmap_size =3D size; >>>>> + >>>>> + /* >>>>> + * Turn on IBT legacy bitmap. >>>>> + */ >>>>> + modify_fpu_regs_begin(); >>>>> + rdmsrl(MSR_IA32_U_CET, r); >>>>> + r |=3D (MSR_IA32_CET_LEG_IW_EN | bitmap); >>>>> + wrmsrl(MSR_IA32_U_CET, r); >>>>> + modify_fpu_regs_end(); >>>>> + >>>>> + return 0; >>>>> +} >>>>=20 >>>> So you just program a random user supplied address into the hardware. >>>> What happens if there's not actually anything at that address or the >>>> user munmap()s the data after doing this? >>>=20 >>> This function checks the bitmap's alignment and size, and anything else i= s >>> the >>> app's responsibility. What else do you think the kernel should check? >>>=20 >>=20 >> One might reasonably wonder why this state is privileged in the first pla= ce >> and, given that, why we=E2=80=99re allowing it to be written like this. >>=20 >> Arguably we should have another prctl to lock these values (until exec) a= s a >> gardening measure. >=20 > We can prevent the bitmap from being set more than once. I will test it. >=20 I think it would be better to make locking an explicit opt-in.=