RE: [PATCH v7 03/10] x86, mpx: add macro cpu_has_mpx

["Ren, Qiaowei" <qiaowei.ren@intel.com>]

On 2014-07-23, Hansen, Dave wrote:
> On 07/20/2014 10:38 PM, Qiaowei Ren wrote:
>> +#ifdef CONFIG_X86_INTEL_MPX
>> +#define cpu_has_mpx boot_cpu_has(X86_FEATURE_MPX) #else #define
>> +cpu_has_mpx 0 #endif /* CONFIG_X86_INTEL_MPX */
> 
> Is this enough checking?  Looking at the extension reference, it says:
> 
>> 9.3.3 Enabling of Intel MPX States An OS can enable Intel MPX states to
>> support software operation using bounds registers with the following
>> steps: * Verify the processor supports XSAVE/XRSTOR/XSETBV/XGETBV
>> instructions and XCR0 by checking CPUID.1.ECX.XSAVE[bit 26]=1.
> 
> That, I assume the xsave code is already doing.
> 
>> * Verify the processor supports both Intel MPX states by checking
> CPUID.(EAX=0x0D, ECX=0):EAX[4:3] is 11b.
> 
> I see these bits _attempting_ to get set in pcntxt_mask via XCNTXT_MASK.
>  But, I don't see us ever actually checking that they _do_ get set.
> For instance, we do this for:
> 
>>         if ((pcntxt_mask & XSTATE_FPSSE) != XSTATE_FPSSE) {
>>                 pr_err("FP/SSE not shown under xsave features
> 0x%llx\n",
>>                        pcntxt_mask);
>>                 BUG();
>>         }

The checking about MPX feature should be as follow:

        if (pcntxt_mask & XSTATE_EAGER) {
                if (eagerfpu == DISABLE) {
                        pr_err("eagerfpu not present, disabling some xstate features: 0x%llx\n",
                                        pcntxt_mask & XSTATE_EAGER);
                        pcntxt_mask &= ~XSTATE_EAGER;
                } else {
                        eagerfpu = ENABLE;
                }
        }

This patch was merged into kernel the ending of last year (https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=e7d820a5e549b3eb6c3f9467507566565646a669 )

Thanks,
Qiaowei

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